Test system with inference circuit

• US 5,737,497 A
• Filed: 09/14/1995
• Issued: 04/07/1998
• Est. Priority Date: 02/25/1993
• Status: Expired due to Fees

• Current Assignee: Reticular Systems Incorporated
• Original Assignee: Reticular Systems Incorporated
• Inventors: Ballard, Dan
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/528,314
• Time in Patent Office: 936 Days
• Field of Search: 371/22.3, 395/183.06, 395/50, 395/10, 395/916, 395/183.02
• US Class Current: 706/47
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06N 5/04 Inference or reasoning models
• CPC Class Codes: G06N 5/046 Forward inferencing; Production systems
• CPC Class Codes: G06N 5/047 Pattern matching networks; Rete networks
• CPC Class Codes: Y10S 706/916 Electronic or computer, internal or network, circuit

Abstract

A rule based processing system that is optimized for implementation in hardware. The system includes a set of logic gates that are used to implement a rule network connected to a working memory composed from a set of memory components. When a set of inputs are presented to the logic gates, a set of inferences are formed and the results are stored in the memory components. The inferences that are stored in the working memory are used to determine the state of the system at any given time. These inferences can be output to an external device to report on the status of the system. The rule based production system is designed to be implementable on a high performance semiconductor micro-chip and is thus suitable for use in embedded real-time applications.

Claims

1. A universal test system, comprising:

a production system processor having an inference circuit, comprising;

a rule network connected to a working memory,

circuitry receiving input data from a bus and applying the input data to the inference circuit, and

circuitry reading output data from the inference circuit and transmitting the output data to the bus; and

a plurality of system circuits containing boundary-scan inputs and outputs in communication with the production system processor over the bus so that the system circuits are tested by the production system processor.

2. The system defined in claim 1, wherein the working memory comprises a plurality of flip flops.

3. The system defined in claim 1, wherein the rule network comprises digital logic indicative of an AND/OR graph.

4. The system defined in claim 1, wherein the boundary-scan inputs and outputs are defined by IEEE Standard Number 1149.

5. In a universal test system having a production system processor with an inference circuit comprising a rule network connected to a working memory and a plurality of system circuits containing boundary-scan inputs and outputs in communication with the production system processor over a bus, a method of testing the system circuits, comprising the steps of:

receiving input data from a bus;

applying the input data to the inference circuit;

inferencing the input data in the inference circuit thereby producing output data;

reading output data from the inference circuit;

transmitting the output data to the bus; and

testing the system circuits over the bus.