Data processing system and method thereof

• US 5,737,586 A
• Filed: 03/21/1995
• Issued: 04/07/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/408,098
• Time in Patent Office: 1,113 Days
• Field of Search: 395/583, 395/800
• US Class Current: 712/236
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A data processor, comprising:

interface means for receiving a data processing instruction, wherein an operand of the data processing instruction is one of a scalar value and a portion of a vector value;

a sequencer for decoding the data processing instruction to provide a plurality of control signals, the sequencer being coupled to the interface means for receiving the data processing instruction;

instruction execution means for executing a data processing operation in response to the plurality of control signals, the instruction execution means providing a result of the data processing operation, the instruction execution means being coupled to the sequencer for receiving the plurality of control signals;

a first storage circuit for storing an overflow value, the overflow value being asserted when the result is not one of a range of data values, the overflow value being negated when the result is one of the range of data values;

a modification circuit coupled to the first storage circuit for receiving the overflow value and coupled to the instruction execution means for receiving the result, the modification circuit modifying the result to be equal to a predetermined value when the overflow value is asserted; and

a second storage circuit for storing an overflow direction value, the overflow direction value being asserted when the result is greater than a maximum value and the overflow direction value being negated when the result is less than a minimum value.

2. The data processor of claim 1 further comprising:

a third storage circuit for providing the operand of the data processing instruction.

3. The data processor of claim 2 wherein the predetermined value is a most positive number when the overflow value is asserted and the overflow direction value is asserted.

4. The data processor of claim 2 wherein the predetermined value is one of a most negative number and zero when the overflow value is asserted and the overflow direction value is negated.

5. The data processor of claim 1 further comprising:

a third storage circuit for storing a sign control value, the sign control value being asserted when the result is a two'"'"'s complement signed data value and the sign control value being negated when the result is an unsigned data value.

6. The data processor of claim 5 wherein the predetermined value is a most positive signed number when the sign control value is asserted, the overflow value is asserted, and the overflow direction value is asserted.

7. The data processor of claim 5 wherein the predetermined value is a most negative signed number when the sign control value is negated, the overflow value is asserted, and the overflow direction value is negated.

8. The data processor of claim 5 wherein the predetermined value is a most positive unsigned number when the sign control value is negated, the overflow value is asserted, and the overflow direction value is asserted.

9. The data processor of claim 5 wherein the predetermined value is equal to zero when the sign control value is negated, the overflow value is asserted, and the overflow direction value is negated.

10. The data processor of claim 1 wherein the first storage circuit comprises a first register bit and the second storage circuit comprises a second register bit.

11. A method for performing saturation on a vector result in a vector processor, comprising the steps of:

receiving a preliminary instruction;

executing the preliminary instruction by performing an operation on a first portion of a vector operand to produce a first portion of the vector result;

receiving a non-preliminary instruction;

executing the non-preliminary instruction by performing the operation on a second portion of the vector operand to produce a second portion of the vector result;

receiving a saturation instruction; and

performing saturation on the first portion of the vector result during execution of the saturation instruction.

12. A method as in claim 11, wherein the saturation instruction has the mnemonic form of "vsat".

13. A method as in claim 11, wherein the second portion of the vector result is never affected by execution of the saturation instruction.

14. A method as in claim 11, wherein the operation is an arithmetic operation.

15. A method for performing saturation in a data processor, comprising the steps of:

storing a result value from a previously executed instruction;

receiving a saturation instruction;

decoding at least a portion of the saturation instruction to provide control signals to control execution of the saturation instruction;

performing steps (a) and (b) during execution of the saturation instruction;

(a) checking status information to determine whether overflow occurred during the previously executed instruction; and

(b) if overflow occurred during the previously executed instruction, replacing the result value with a predetermined bound value.

16. A method as in claim 15, further comprising the steps of:

if overflow occurred during the previously executed instruction, checking the status information during execution of the saturation instruction to determine a direction for the overflow.

17. A method as in claim 15, further comprising the steps of:

checking status information during execution of the saturation instruction to determine if the result value is a signed number.

18. A method as in claim 15, wherein the result value is a vector value.

19. A data processor, comprising:

a vector engine capable of executing a vector operation in response to a vector instruction;

a scalar engine capable of executing a scalar operation in response to a scalar instruction;

instruction circuitry for receiving at least the vector instruction and the scalar instruction, for providing the vector instruction to said vector engine, and for providing the scalar instruction to said scalar engine;

interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine;

wherein the vector engine comprises;

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

vector control circuitry for controlling operation of that one of the plurality of processing elements;

arithmetic circuitry for performing an arithmetic operation;

a storage circuit for storing an overflow value, the overflow value indicating if a result is not within a predetermined range; and

a modification circuit coupled to the storage circuit for receiving the overflow value, the modification circuit modifying the result to be equal to a predetermined value when the overflow value indicates that the result is not within the predetermined range.

20. A data processor as in claim 19, wherein the scalar engine comprises:

a scalar execution unit for executing the scalar instruction, said scalar execution unit comprising;

scalar control circuitry for controlling operation of said scalar execution unit;

scalar arithmetic circuitry for performing an arithmetic operation;

a scalar storage circuit for storing a scalar overflow value, the scalar overflow value indicating if a scalar result is not within a second predetermined range; and

a scalar modification circuit coupled to the scalar storage circuit for receiving the scalar overflow value, the scalar modification circuit modifying the scalar result to be equal to a predetermined scalar value when the scalar overflow value indicates that the scalar result is not within the second predetermined range.