Reprogrammable instruction set accelerator

• US 5,737,631 A
• Filed: 04/05/1995
• Issued: 04/07/1998
• Est. Priority Date: 04/05/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): KING, CONLEY BURRELL
• Application Number:
  US08/417,337
• Time in Patent Office: 1,098 Days
• Field of Search: 395/430, 395/384, 395/385, 395/386, 395/387, 395/388, 395/389, 395/800.37, 395/376, 326/39
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources. A condition code register is coupled to instruction fetching resources, and connected to receive condition codes from both the defined execution unit and from the programmable execution unit. The programmable execution unit includes logic to signal the instruction fetching resources to provide a next instruction when execution of the programmed instruction is done. Resources for accessing the configuration store to program the programmable execution unit are provided, which can utilize the internal buses of the data processor or be completely independent of them.

Claims

1. A data processor comprising:

internal buses for operand and result data;

a defined execution unit coupled to the internal buses for execution of defined instructions;

a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and

a condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit.

2. The data processor of claim 1, wherein at least one internal bus is divided into a first section and a second section, wherein the first section is coupled to the defined execution unit and not the programmable execution unit, and wherein the second section is coupled to the programmable execution unit and not the defined execution execution unit.

3. The data processor of claim 1, wherein at least one internal bus is divided into two sections, thereby allowing the defined execution unit and the programmable execution unit to share input signals and yet provide independent output signals to the at least one internal bus.

4. The data processor of claim 1, wherein the internal buses include a first bus and a second bus, and the defined execution unit and the programmable execution unit are connected in parallel across the first and second buses.

5. The data processor of claim 1, wherein the programmable execution unit comprises a field programmable gate array.

6. The data processor of claim 1, including:

an instruction register which holds a current instruction for execution, and an instruction data path supplying the instruction to the defined execution unit and to the programmable execution unit, wherein each said instruction is characterized by a plurality of instruction fields.

7. The data processor of claim 6, wherein the instruction data path includes a decoder.

8. The data processor of claim 6, wherein the instructions have a prespecified format, including an opcode field specifying an operation by one of the defined and programmable execution units.

9. The data processor of claim 8, wherein the prespecified format includes a defined/programmed flag, specifying a defined or a programmed instruction.

10. The data processor of claim 8, wherein the prespecified format includes an immediate data field, and programmed instructions use the immediate data field to identify a programmed operation and the opcode field to identify the instruction as a programmed instruction.

11. The data processor of claim 6, wherein the instructions have a prespecified format, including a defined opcode field for specifying an operation by the defined execution unit, and a programmed opcode field for specifying a programmed operation by the programmable execution unit.

12. The data processor of claim 6, wherein all fields of the instructions are provided to the programmable execution unit.

13. The data processor of claim 1, including:

an instruction fetching resources responsive to condition codes; and

a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.

14. The data processor of claim 1, including:

an instruction state machine; and

the programmable execution unit includes logic to signal the instruction state machine when execution of a programmed instruction is done.

15. The data processor of claim 1, wherein the programmable execution unit receives programming information through the internal buses.

16. The data processor of claim 1, wherein the programmable execution unit receives programming information through a configuration port independent of the internal buses.

17. The data processor of claim 1, including:

logic which indicates that the programmable execution unit is being configured.

18. The data processor of claim 1, including:

a register file, coupled to the internal buses, accessible by both the defined execution unit and the programmable execution unit.

19. The data processor of claim 1, including a set of registers dedicated for use by the defined execution unit.

20. The data processor of claim 1, including a set of registers dedicated for use by the programmable execution unit.

21. The data processor of claim 1, including a data port coupled to the programmable execution unit.

22. The data processor of claim 21, wherein the data port comprises a source of operand data for the programmable execution unit, independent of the internal buses.

23. The data processor of claim 21, wherein the data port comprises a destination of operand data for the programmable execution unit, independent of the internal buses.

24. A microprocessor, comprising:

internal buses for operand and result data;

a defined execution unit coupled to the internal buses for execution of defined instructions;

a programmable execution unit coupled to the internal buses for execution of a programmed instruction;

resources for accessing the programmable execution unit to define programmed instructions;

an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit;

an instruction state machine, responsive to condition codes, which supply instructions to the instruction register; and

a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.

25. The microprocessor of claim 24, wherein the programmable execution unit comprises field programmable gate array logic having a configuration store, and the resources for accessing the programmable execution unit include a data path to the configuration store to program the programmable execution unit through the internal buses.

26. The microprocessor of claim 24, wherein the programmable execution unit comprises field programmable gate array logic having a configuration store, and the resources for accessing the programmable execution unit include a configuration port independent of the internal buses for accessing the configuration store to program the programmable execution unit.

27. The microprocessor of claim 24, wherein:

the programmable execution unit includes logic to signal the instruction state machine when execution of a programmed instruction is done.

28. The microprocessor of claim 24, wherein the instructions have a prespecified format, including an opcode field specifying an operation by one of the defined and programmable execution units.

29. The microprocessor of claim 28, wherein the prespecified format includes a defined/programmed flag, specifying a defined or a programmed instruction.

30. The microprocessor of claim 28, wherein the prespecified format includes an immediate data field, and programmed instructions use the immediate data field to identify a programmed operation and the opcode field to identify the instruction as a programmed instruction.

31. The microprocessor of claim 24, wherein the instructions have a prespecified format, including a defined opcode field for specifying an operation by the defined execution unit, and a programmed opcode field for specifying a programmed operation by the programmable execution unit.

32. The microprocessor of claim 24, wherein the internal buses include a first bus and a second bus, and the defined execution unit and the programmable execution unit are connected in parallel across the first and second buses.

33. The microprocessor of claim 24, including:

logic which indicates that the programmable execution unit is being configured.

34. The microprocessor of claim 24, including:

a register file, coupled to the internal buses, accessible by both the defined execution unit and the programmable execution unit.

35. The microprocessor of claim 24, including a set of registers dedicated for use by the defined execution unit.

36. The microprocessor of claim 24, including a set of registers dedicated for use by the programmable execution unit.

37. The microprocessor of claim 24, including a data port coupled to the programmable execution unit comprising a source of operand data for the programmable execution unit, independent of the internal buses.

38. The microprocessor of claim 24, including a data port coupled to the programmable execution unit comprising a destination of operand data for the programmable execution unit, independent of the internal buses.

39. A data processor comprising:

internal buses for operand and result data;

a defined execution unit coupled to the internal buses for execution of defined instructions;

a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and

a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the data processor.

40. A microprocessor, comprising:

internal buses for operand and result data;

a defined execution unit coupled to the internal buses for execution of defined instructions;

a programmable execution unit coupled to the internal buses for execution of a programmed instruction;

resources for accessing the programmable execution unit to define programmed instructions;

an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit;

an instruction state machine, responsive to condition codes, which supply instructions to the instruction register;

a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit; and

a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the microprocessor.