Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory

• US 5,737,748 A
• Filed: 03/15/1995
• Issued: 04/07/1998
• Est. Priority Date: 03/15/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shigeeda, Akio
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/404,702
• Time in Patent Office: 1,119 Days
• Field of Search: 395/449, 395/469, 395/468, 395/470, 395/497.01, 395/497.03, 395/462, 395/461
• US Class Current: 711/122
• CPC Class Codes: G06F 1/1616 with folding flat displays, e.g. laptop computers or notebooks having a clamshell configuration, with body parts pivoting to an open position around an axis parallel to the plane they define in closed position
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An electronic device for use in a computer system, and having a small second-level write-back cache, is disclosed. The device may be implemented into a single integrated circuit, as a microprocessor unit, to include a microprocessor core, a memory controller circuit, and first and second level caches. In a system implementation, the device is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access that is a cache hit in the second level cache writes to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed. In addition, each entry of the second level cache is flushed to DRAM upon each of its byte locations being modified. The computer system may also include one or more additional integrated circuit devices, such as a direct memory access (DMA) circuit and a bus bridge interface circuit for bidirectional communication with the microprocessor unit. The microprocessor unit may also include handshaking control to prohibit configuration register updating when a memory access is in progress or is imminent. The disclosed microprocessor unit also includes circuitry for determining memory bank size and memory address type.

Claims

1. A microprocessor unit, comprising:

a microprocessor having a processing unit operable to process digital data in accordance with computer instructions, and having a first cache of a selected capacity, said first cache being of write-through type, and coupled to said processing unit;

a second cache having a plurality of cache entries of a cumulative capacity that is substantially smaller than the capacity of said first cache, said second cache being of write-back type, and having a plurality of dirty bits, each associated with one of the plurality of cache entries for indicating, when set, that data in its associated cache entry has been modified, and said second cache coupled to said first cache at a higher cache level; and

memory control circuitry, for applying the contents of the plurality of entries of the second cache to a memory bus, responsive to all of the plurality of dirty bits of the second cache being set.

2. The microprocessor unit of claim 1, wherein the microprocessor, second cache, and memory control circuitry are implemented into a single integrated circuit device.

3. The microprocessor unit of claim 1, wherein each of the cache entries of the second cache comprises a plurality of byte locations;

and wherein the memory control circuitry is also for applying the contents of a cache entry to the memory bus responsive to all of the byte locations in the cache entry being modified.

4. The microprocessor unit of claim 1, wherein the second cache is also for storing, in each of the plurality of cache entries, a bank select value associated with a memory address,

and wherein the memory control circuitry is also for generating a bank select signal responsive to the bank select value, in accessing a multiple bank memory via the memory bus.

5. The microprocessor unit of claim 1 wherein the capacity of said first cache is at least 1K byte.

6. The microprocessor unit of claim 5 wherein the capacity of said second cache is less than or equal to 64 bytes.

7. A microprocessor unit, comprising:

a microprocessor having a processing unit operable to process digital data in accordance with computer instructions;

a first cache comprising;

write-through cache control circuitry; and

a first cache storage area for data and instructions, and coupled to said processing unit; and

a second cache comprising;

a second cache storage area substantially smaller than the first cache storage area, arranged as a plurality of cache entries, coupled to said first cache, at a higher cache level, and to said processing unit, and having a plurality of dirty bits, each associated with one of the plurality of cache entries, for indicating, when set, that its associated cache entry has been modified; and

write-back cache control circuitry for applying the contents of the plurality of entries of the second cache storage area to a memory bus responsive to all of the plurality of dirty bits being set.

8. The microprocessor unit of claim 7, wherein the microprocessor, first cache, and second cache are implemented into a single integrated circuit device.

9. The microprocessor unit of claim 7, wherein each of the cache entries of the second cache storage area comprises a plurality of byte locations;

and wherein the write-back cache control circuitry is also for applying the contents of a cache entry to the memory bus responsive to all of the byte locations in the cache entry being modified.

10. The microprocessor unit of claim 7, wherein the second cache storage area is also for storing, in each of the plurality of cache entries, a bank select value associated with a memory address,

and wherein the write-back cache control circuitry is also for generating a bank select signal responsive to the bank select value, in accessing a multiple bank memory via the memory bus.

11. The microprocessor unit of claim 9, wherein the first cache storage area exceeds one kilobyte.

12. The microprocessor unit of claim 11, wherein the second cache storage area is less than or equal to 64 bytes.