Generation of memory column addresses using memory array type bits in a control register of a computer system

• US 5,737,764 A
• Filed: 06/07/1995
• Issued: 04/07/1998
• Est. Priority Date: 03/15/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shigeeda, Akio
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/474,582
• Time in Patent Office: 1,035 Days
• Field of Search: 395/497.01, 395/497.02, 395/497.03, 395/421.01, 395/421.02, 395/886, 395/307, 395/308, 395/309, 395/310, 395/283, 395/285, 395/490, 395/494, 395/651 , 395/653, 395/828, 395/829, 395/830, 395/833
• US Class Current: 711/170
• CPC Class Codes: G06F 1/1616 with folding flat displays, e.g. laptop computers or notebooks having a clamshell configuration, with body parts pivoting to an open position around an axis parallel to the plane they define in closed position
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method and circuitry for generating column addresses for a memory based upon signals on an address bus in a computer system, are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access memory (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.

Claims

1. A memory controller circuit for generating column addresses from addresses communicated on a bus, comprising:

a control register for storing a memory array type code indicating a particular one of a plurality of memory array types; and

a column address selector circuit having inputs receiving a plurality of address lines of the bus, having outputs, and having control inputs receiving the contents of said control register, for selectively communicating a number of the address lines to its outputs as a column address responsive to the memory array type code stored in said control register.

2. The circuit of claim 1 wherein said control register comprises a plurality of locations, each control register location storing a memory array type code associated with one of a plurality of banks of a memory to be addressed by the column addresses;

and further comprising;

a bank control selector having inputs coupled to each of the locations of the control register, having outputs coupled to the control inputs of the column address selector circuit, and having control inputs receiving a bank identification signal, the bank control selector for selectively passing, to the control inputs of the column address selector circuit, the memory array type code for the bank identified by the bank identification signal.

3. The circuit of claim 1 further comprising:

a row address selector circuit having inputs receiving a plurality of address lines of the bus, having outputs, and having control inputs receiving the contents of said control register, for selectively communicating a number of the address lines to its outputs as a row address responsive to the memory array type code stored in said control register.

4. The circuit of claim 3 wherein said control register comprises a plurality of locations, each control register location storing a memory array type code associated with one of a plurality of banks of a memory to be addressed by the row and column addresses;

and further comprising;

a bank control selector having inputs coupled to each of the locations of the control register, having outputs coupled to the control inputs of the column address selector circuit and to the control inputs of the row address selector circuit, and having control inputs receiving a bank identification signal, the bank control selector for selectively passing, to the control inputs of the column address selector circuit and to the control inputs of the row address selector circuit, the memory array type code for the bank identified by the bank identification signal.

5. The circuit of claim 3 further comprising a row/column address multiplexer having inputs connected to the outputs of the column address selector circuit and to the outputs of the row address selector circuit, and having outputs to supply multiplexed row/column addresses.

6. The circuit of claim 1, wherein the column address selector circuit has a first set of inputs coupled to address lines of the bus, and has a second set of inputs including at least one input connected to a fixed level;

and wherein the column address selector circuit communicates its first set of inputs to its outputs responsive to the memory array type code having a first value, and communicates its second set of inputs to its outputs responsive to the memory array type code having a second value.

7. The circuit of claim 6, wherein the column address selector circuit forwards a least-significant group of address lines of the bus to its outputs responsive to the memory array type code having either the first or second value.

8. A method of operating a memory controller circuit to generate row and column addresses for a memory, comprising the steps of:

storing a memory array type code in a control register, the memory array type code indicating a particular one of a plurality of memory array types;

receiving a memory address on a plurality of address lines of a bus;

generating a row address from a first plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register; and

generating a column address from a second plurality of address lines of the bus, selected responsive to the memory array type code stored in the control register.

9. The method of claim 8 wherein the memory array type code indicates the number of column address bits to be applied to the memory in a memory access.

10. The method of claim 8, wherein the memory is arranged in a plurality of banks;

wherein the storing step comprises storing a memory array type code in each of a plurality of locations of the control register, each location associated with one of the plurality of banks of the memory;

and further comprising;

before the generating steps, selecting one of the plurality of locations of the control register responsive to a bank select signal.

11. The method of claim 8, further comprising:

applying the row address to a memory; and

applying the column address to the memory.

12. The method of claim 8, further comprising:

applying the row address to a memory address bus; and

applying the column address to the memory address bus.

13. The method of claim 12, wherein the step of applying the column address is performed after the step of applying the row address.

14. The method of claim 8, wherein the step of generating a column address comprises:

generating a first portion of the column address from a first group of address lines of the bus;

generating a second portion of the column address, the second portion being of greater significance than the first portion, from a second group of address lines of the bus responsive to the memory array type code having a first value; and

generating the second portion of the column address to have at least one bit with a fixed value responsive to the memory array type code having a second value.

15. The method of claim 14, wherein the step of generating a row address comprises:

selecting a third group of address lines of the bus responsive to the memory array type code having the first value; and

selecting a fourth group of address lines of the bus, the second group having at least one address line of the bus not within the first group of address lines of the bus, responsive to the memory array type code having the second value.