Electronic system with circuitry for selectively enabling access to configuration registers used by a memory controller
First Claim
1. An electronic system comprising:
- a memory; and
a microprocessor unit coupled to the memory and to a system bus, the microprocessor unit comprising;
a memory controller circuit coupled to said memoryconfiguration registers for storing configuration information for use by said memory controller circuit in performing accesses to the memory; and
a bus bridge circuit coupled to said system bus for transferring addresses and data, and comprising;
a request logic circuit for generating, responsive to at least one of the addresses, a write request signal to said memory controller circuit signaling an impending write access to at least one of said configuration registers; and
an enable circuit for enabling a write access to at least one of said configuration registers responsive to receiving a reply signal;
wherein said memory controller circuit includes a reply logic circuit for generating the reply signal responsive to the combination of the write request signal from said request logic circuit and a signal in the memory controller indicating the absence of a pending memory operation utilizing current information in at least one of said configuration registers.
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Abstract
An electronic system, such as a computer system, in which access to configuration registers used by a memory controller, is selectively enabled. The disclosed system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed. The request logic includes an enable circuit responsive to the reply output to then enable the impending access to the configuration registers. The electronic system may also include one or more additional integrated circuit devices, such as may include a direct memory access (DMA) circuit and a bus bridge interface circuit for bidirectional communication with the microprocessor unit. The microprocessor unit may also include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for determining memory bank size and memory address type.
68 Citations
20 Claims
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1. An electronic system comprising:
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a memory; and a microprocessor unit coupled to the memory and to a system bus, the microprocessor unit comprising; a memory controller circuit coupled to said memory configuration registers for storing configuration information for use by said memory controller circuit in performing accesses to the memory; and a bus bridge circuit coupled to said system bus for transferring addresses and data, and comprising; a request logic circuit for generating, responsive to at least one of the addresses, a write request signal to said memory controller circuit signaling an impending write access to at least one of said configuration registers; and an enable circuit for enabling a write access to at least one of said configuration registers responsive to receiving a reply signal; wherein said memory controller circuit includes a reply logic circuit for generating the reply signal responsive to the combination of the write request signal from said request logic circuit and a signal in the memory controller indicating the absence of a pending memory operation utilizing current information in at least one of said configuration registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer system, comprising:
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a memory; a microprocessor unit coupled to the memory and to a system bus, the microprocessor unit comprising; a microprocessor having a processing unit operable to process digital data in accordance with computer instructions; a memory controller circuit coupled to the memory and to the microprocessor; configuration registers for storing configuration information for use by said memory controller circuit in performing accesses to the memory; and a bus bridge circuit coupled to the system bus and to the microprocessor, for transferring addresses and data, and comprising; a request logic circuit for generating, responsive to at least one of the addresses, a write request signal to said memory controller circuit signaling an impending write access to at least one of said configuration registers; and an enable circuit for enabling a write access to at least one of said configuration registers responsive to receiving a reply signal; wherein said memory controller circuit includes a reply logic circuit for generating the reply signal responsive to the combination of the write request signal from said request logic circuit and a signal in the memory controller indicating the absence of a pending memory operation utilizing current information in at least one of said configuration registers; and wherein the computer system further comprises; a peripheral processor unit coupled to said microprocessor unit and having circuitry for bidirectional data communication therewith; a user input interface coupled to the peripheral processor unit; and an output interface coupled to the peripheral processor unit. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification