Semiconductor processing methods of forming a conductive gate and line

• US 5,739,066 A
• Filed: 09/17/1996
• Issued: 04/14/1998
• Est. Priority Date: 09/17/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Pan, Pai-Hung
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Mee, Brendan
• Application Number:
  US08/710,353
• Time in Patent Office: 574 Days
• Field of Search: 438/595, 438/303
• US Class Current: 438/595
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence

Abstract

A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision and subsequent anisotropic etch of a first insulating material, followed by provision and subsequent anisotropic etch of a second insulating material.

Claims

1. A semiconductor processing method of forming a conductive transistor gate over a substrate comprising the steps of:

forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls which join with the gate dielectric layer and the gate having an interface with the gate dielectric layer;

forming nitride containing spacers over the respective entireties of the gate sidewalls, the spacers joining with the gate dielectric layer; and

after forming the spacers, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer.

2. The semiconductor processing method of claim 1, wherein the gate comprises a first conductive layer a portion of which defines the interface, an overlying metal, and an electrically conductive reaction barrier layer interposed between the first layer and the overlying metal.

3. The semiconductor processing method of claim 1, wherein the gate comprises polysilicon, an overlying metal, and an electrically conductive reaction barrier layer intermediate the polysilicon and the overlying metal.

4. The semiconductor processing method of claim 1, wherein the step of forming the nitride containing spacers includes:

depositing a first nitride containing material over the gate;

depositing a second nitride containing material over the first nitride containing material; and

anisotropically etching the first and second nitride containing materials to a degree sufficient to leave the spacers over the gate sidewalls, the spacers being defined by both first and second nitride containing material.

5. The semiconductor processing method of claim 1, wherein the step of forming the nitride containing spacers includes:

depositing a first nitride containing material over the gate;

anisotropically etching the first nitride containing material to a degree sufficient to leave first nitride containing spacers over the gate sidewalls;

depositing a second nitride containing material over the first nitride containing spacers; and

anisotropically etching the second nitride containing material to a degree sufficient to leave second nitride containing spacers proximate the first nitride containing spacers.

6. The semiconductor processing method of claim 1, including:

depositing a first nitride containing material over the gate;

anisotropically etching the first nitride containing material to a degree sufficient to leave first nitride containing spacers over the gate sidewalls; and

further comprising after the exposing of the substrate to the oxidizing conditions;

depositing a second nitride containing material over the first nitride containing spacers; and

anisotropically etching the second nitride containing material to a degree sufficient to leave second nitride containing spacers proximate the first nitride containing spacers.

7. The semiconductor processing method of claim 1, wherein the oxidizing conditions include an ambient temperature in the range from between about 800°

C. to 1050°

C.

8. The semiconductor processing method of claim 1, wherein the gate includes a gate top and further comprising prior to exposing the substrate to the oxidizing conditions, forming an oxidation resistant material over the gate top which, together with the nitride containing spacers, effectively encapsulates the gate.

9. The semiconductor processing method of claim 1, wherein the gate includes a gate top and further comprising prior to exposing the substrate to the oxidizing conditions, forming an nitride containing oxidation resistant material over the gate top which, together with the nitride containing spacers, effectively encapsulates the gate.

10. A semiconductor processing method of forming a conductive gate comprising conducting a gate oxidation step after encapsulating the gate with oxidation resistant material,

said encapsulating comprising forming an oxidation resistant material over the gate and anisotropically etching the material to provide sidewall spacers over sidewalls of the gate, and

said conducting comprising channeling oxidants through a layer which underlies the gate and sidewall spacers and which is outwardly exposed laterally proximate the sidewall spacers.

11. The semiconductor processing method of claim 10, wherein the step of encapsulating the gate comprises forming electrically insulative sidewall spacers over the gate by:

depositing a first insulative material over the gate;

depositing a second insulative material over the first insulative material; and

anisotropically etching the first and second insulative materials to a degree sufficient to leave the insulative spacers over the gate.

12. The semiconductor processing method of claim 10, wherein the step of encapsulating the gate comprises forming electrically insulative sidewall spacers over the gate by:

depositing a first insulative material over the gate;

anisotropically etching the first insulative material to a degree sufficient to leave first insulative spacers over the gate;

depositing a second insulative material over the first insulative spacers; and

anisotropically etching the second insulative material to a degree sufficient to leave second insulative spacers over the first insulative spacers.

13. The semiconductor processing method of claim 10, wherein the gate comprises polysilicon, an overlying metal, and an electrically conductive reaction barrier layer intermediate the polysilicon and the overlying metal.

14. The semiconductor processing method of claim 10, wherein the oxidation resistant material contains a nitride material.

15. The semiconductor processing method of claim 10, wherein the gate has a gate top and the encapsulating step comprises forming a nitride containing oxidation resistant material over the gate sidewalls and gate top.

16. A semiconductor processing method of forming a conductive transistor gate over a substrate comprising the steps of:

forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls;

forming non-oxide material over the gate and dielectric layer;

anisotropically etching the non-oxide material to form non-oxide spacers over the sidewalls which join with the gate dielectric layer; and

after anisotropically etching the non-oxide material to form the spacers, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate and a portion of the substrate beneath the gate.

17. The semiconductor processing method of claim 16, wherein the step of forming the non-oxide spacers comprises:

depositing a first non-oxide material over the gate and sidewalls; and

depositing a second non-oxide material over the first non-oxide material prior to the anisotropic etching of the non-oxide material.

18. The semiconductor processing method of claim 16, wherein the forming the non-oxide material and the anisotropically etching therof comprises:

depositing a first non-oxide material over the gate;

anisotropically etching the first non-oxide material to a degree sufficient to leave first spacers over the gate sidewalls;

depositing a second non-oxide material over the first spacers; and

anisotropically etching the second non-oxide material to a degree sufficient to leave second spacers over the first spacers.

19. The semiconductor processing method of claim 16, wherein the oxidizing conditions include an ambient temperature from between about 800°

C. to 1050°

C.

20. A semiconductor processing method of forming a conductive transistor gate comprising the steps of:

forming a conductive gate stack over a gate dielectric layer on a substrate;

the stack comprising polysilicon, an overlying metal, and an electrically conductive reaction barrier layer intermediate the polysilicon and the overlying metal;

the gate having sidewalls and an interface with the gate dielectric layer;

forming an oxidation resistant layer over at least the gate stack sidewalls of all of the metal and polysilicon, none of the polysilicon being outwardly exposed; and

after forming the oxidation resistant layer, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate laterally adjacent the oxidation resistant layer.

21. The semiconductor processing method of claim 20, wherein the oxidation resistant layer effectively encapsulates the gate stack.

22. The semiconductor processing method of claim 20, wherein the oxidation resistant layer comprises a nitride material.

23. The semiconductor processing method of claim 20, wherein the oxidation resistant layer comprises an oxidation resistant cap atop the overlying metal, and the step of forming the oxidation resistant layer over at least the gate stack sidewalls of the metal comprises:

depositing a first oxidation resistant layer over the gate;

depositing a second oxidation resistant layer over the first oxidation resistant layer; and

anisotropically etching the first and second layers, material of both layers being etched to a degree sufficient to leave sidewall spacers over at least the gate stack sidewalls between the cap and the dielectric layer.

24. The semiconductor processing method of claim 20, wherein the oxidation resistant layer further comprises an oxidation resistant cap atop the overlying metal, and the step of forming the oxidation resistant layer over at least the gate stack sidewalls of the metal comprises:

depositing a first oxidation resistant layer over the gate;

anisotropically etching the first oxidation resistant layer to a degree sufficient to leave first sidewall spacers over at least the gate stack sidewalls between the cap and the dielectric layer;

depositing a second oxidation resistant layer over the first sidewall spacers; and

anisotropically etching the second oxidation resistant layer to a degree sufficient to leave second sidewall spacers over at least most of the first sidewall spacers.

25. The semiconductor processing method of claim 20, wherein the oxidation resistant layer further comprises an oxidation resistant cap atop the overlying metal, comprising:

depositing a first oxidation resistant layer over the gate;

anisotropically etching the first oxidation resistant layer to a degree sufficient to leave first sidewall spacers over at least the gate stack sidewalls between the cap and the dielectric layer; and

further comprising after the exposing of the substrate to the oxidizing conditions;

depositing a second oxidation resistant layer over the first oxidation resistant layer; and

anisotropically etching the second oxidation resistant layer to a degree sufficient to leave second sidewall spacers over at least most of the first sidewall spacers.

26. The semiconductor processing method of claim 20, wherein the oxidizing conditions include an ambient temperature condition from between about 800°

C. to 1050°

C.

27. A semiconductor processing method of forming a conductive gate comprising:

forming a gate over a gate dielectric layer on a substrate, the gate having sidewalls;

shielding at least a portion of the gate sidewalls with a nitride containing oxidation resistant material which is disposed directly on the gate dielectric layer; and

after the shielding, exposing the substrate to oxidation conditions effective to oxidize at least a portion of the gate sidewalls laterally inwardly of the oxidation resistant material, the shielding channeling oxidants through the gate dielectric layer to the gate sidewalls.

28. The semiconductor processing method of claim 27, wherein the shielding step comprises covering a top of the gate with the oxidation resistant material.

29. The semiconductor processing method of claim 27, wherein the shielding step comprises covering the gate with the oxidation resistant material in at least two separate steps.

30. The semiconductor processing method of claim 27, wherein the gate comprises polysilicon, an overlying metal, and an electrically conductive reaction barrier layer intermediate the polysilicon and the overlying metal.

31. The semiconductor processing method of claim 27, wherein the gate comprises polysilicon, an overlying metal, and an electrically conductive reaction barrier layer intermediate the polysilicon and the overlying metal, a portion of the overlying metal defining a gate top, and the shielding step further comprises forming an oxidation resistant cap atop the gate top.

32. The semiconductor processing method of claim 27, wherein the oxidizing conditions include an ambient temperature from between about 800°

C. to 1050°

C.

33. A semiconductor processing method of forming a conductive gate comprising the steps of:

forming a patterned gate atop a substrate dielectric surface, at least a portion of the gate being conductive;

covering a top and sidewalls of the gate with oxidation resistant material, said sidewalls being completely covered with said oxidation resistant material; and

after the covering of the sidewalls and with no conductive portion of the gate being exposed, exposing the substrate to oxidation conditions effective to oxidize at least a portion of the gate laterally adjacent the covered sidewalls adjacent the dielectric surface.

34. The semiconductor processing method of claim 33, wherein the conductive portion of the gate comprises a reaction barrier layer and an overlying metal thereon.

35. The semiconductor processing method of claim 33, wherein the conductive portion of the gate comprises polysilicon, an overlying metal, and a reaction barrier layer interposed between the polysilicon and the overlying metal.

36. The semiconductor processing method of claim 33, wherein the covering step comprises:

depositing a first barrier material over the gate;

depositing a second barrier material over the first barrier material; and

anisotropically etching the first and second barrier materials to a degree sufficient to leave the oxidation barriers on the gate.

37. The semiconductor processing method of claim 33, wherein the covering step comprises:

depositing a first barrier material over the gate;

depositing a second barrier material over the first barrier material; and

anisotropically etching the first and second barrier materials to a degree sufficient to leave the oxidation barriers on the gate, the etched first barrier material defining at least one L-shaped oxidation barrier.

38. The semiconductor processing method of claim 33, wherein the covering step comprises:

depositing a first barrier material over the gate;

anisotropically etching the first barrier material to a degree sufficient to leave first oxidation barriers on the gate;

depositing a second barrier material over the first barrier material; and

anisotropically etching the second barrier material to a degree sufficient to leave second oxidation barriers over the first oxidation barriers.

39. The semiconductor processing method of claim 33, wherein the oxidation resistant material comprises a nitride material.

40. A semiconductor processing method of forming a conductive line comprising:

forming a conductive line atop a substrate dielectric layer;

covering a top and sidewalls of the conductive line with at least one nitride material and anisotropically etching said material to provide sidewall spacers which completely cover said sidewalls; and

after the covering of the top and sidewalls, oxidizing a portion of the conductive line laterally inwardly of the nitride material.

41. A semiconductor processing method of forming a conductive transistor gate over a substrate comprising the steps of:

forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls which join with the gate dielectric layer and the gate further having an interface with the gate dielectric layer;

forming a first nitride containing material over the substrate and gate to a thickness ranging from between 50 to 500 Angstroms;

anisotropically etching the first nitride containing material to a degree sufficient to leave first sidewall spacers over the respective entireties of the gate sidewalls, the spacers joining with the gate dielectric layer and having respective outwardly exposed sidewall surfaces;

forming a second nitride containing material over the substrate and outwardly exposed sidewalls surfaces of the first sidewall spacers;

anisotropically etching the second nitride containing material to a degree sufficient to leave second sidewall spacers respectively over the outwardly exposed sidewall surfaces of the first sidewall spacers, the second sidewall spacers completely covering exposed sidewall surfaces of the first sidewall spacers; and

after the etching of the second nitride containing material and with no portion of the gate being exposed, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer by channeling oxidants through the gate dielectric layer, said oxidants entering the gate dielectric layer through exposed portions thereof and being channeled underneath both the first and second sidewall spacers.