Thin film transistor having offset region

• US 5,739,549 A
• Filed: 11/18/1996
• Issued: 04/14/1998
• Est. Priority Date: 06/14/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Konuma, Toshimitsu, Takemura, Yasuhiko
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/751,559
• Time in Patent Office: 512 Days
• Field of Search: 257/57, 257/59, 257/72, 257/351, 257/347, 257/66, 359/54, 359/59, 359/87, 359/88, 349/42, 349/43
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

There is provided an aluminum gate type thin film transistor integrated circuit having a matrix region and a region in which driving circuits thereof are formed wherein impurity regions are selectively formed on a semiconductor thin film in the form of islands and a gate insulation film is formed to cover the impurity regions. Further, a thermal annealing or an optical annealing is performed on the impurity regions and regions in which channels are to be formed adjacent thereto and the gate insulation film to improve the characteristics of those regions themselves and to eliminate discontinuity at the boundaries between those regions. After the above-described steps, gate electrodes are formed. An anodic oxide is provided at least at the portion of a gate electrode provided in the matrix region where it intersects with a line in the layer above it to prevent the gate electrode from shorting with the line.

Claims

1. A semiconductor device comprising:

a semiconductor region formed over an insulating substrate;

impurity regions formed in said semiconductor region;

a gate insulating film formed on said semiconductor region; and

a gate electrode formed on said gate insulating film;

wherein one of said impurity regions is spaced apart from said gate electrode and the other of said impurity regions is overlapped with said gate electrode, and

wherein edges of the impurity regions are substantially vertically provided.

2. The device of claim 1 wherein an anodic oxide film is formed on a surface of said gate electrode.

3. The device of claim 2 wherein said anodic oxide film is a barrier type.

4. The device of claim 2 wherein said anodic oxide film comprises an aluminum oxide.

5. The device of claim 1 wherein said gate electrode comprises aluminum.

6. A semiconductor device comprising:

a semiconductor region formed over an insulating substrate;

impurity regions formed in said semiconductor region;

a gate insulating film formed on said semiconductor region;

a gate electrode formed on said gate insulating film; and

an anodic oxide film formed on a surface of said gate electrode;

wherein one of said impurity regions is spaced apart from said gate electrode and said anodic oxide film; and

the other of said impurity regions is overlapped with said gate electrode and said anodic oxide film, and

wherein edges of the impurity regions are substantially vertically provided.

7. The device of claim 6 wherein said gate electrode comprises aluminum.

8. The device of claim 6 wherein said anodic oxide film is a barrier type.

9. The device of claim 6 wherein said anodic oxide film comprises an aluminum oxide.

10. A semiconductor device comprising;

a semiconductor region formed over an insulating substrate;

a pair of impurity regions and a channel region formed in said semiconductor region;

a gate insulating film on said semiconductor region;

a gate electrode formed on said gate insulating film; and

an anodic oxide film formed on a surface of said gate electrode;

wherein a boundary between one of said impurity regions and said channel region is located below said gate electrode while a boundary between the other one of said impurity regions and said channel region is outwardly offset from said gate electrode.

11. The device of claim 10 wherein said gate electrode comprises aluminum.

12. The device of claim 10 wherein said anodic oxide film is a barrier type.

13. The device of claim 10 wherein said anodic oxide film comprises an aluminum oxide.

14. A semiconductor device comprising;

a semiconductor region formed over an insulating substrate;

a pair of impurity regions formed in said semiconductor region;

a gate insulating film formed on said semiconductor region;

a gate electrode formed on said gate insulating film;

a gate line formed adjacent to said gate electrode, said gate line being formed on said insulating film and over one of said impurity regions;

a first anodic oxide film formed on a surface of said gate line; and

a pixel electrode formed over said gate line;

wherein a first capacitor is constituted of said one impurity region, said gate insulating film and said gate line; and

a second capacitor is constituted of at least said gate line, said first anodic oxide and said pixel electrode,

wherein both of said impurity regions are spaced apart from said gate electrode.

15. The device of claim 14 wherein a second anodic oxide film is formed on a surface of said gate electrode.

16. The device of claim 15 wherein both of said impurity regions are spaced apart from said second anodic oxide film.

17. A semiconductor device comprising:

a semiconductor region formed over an insulating substrate;

source and drain regions formed in the semiconductor region, said source and drain regions being introduced with impurities;

a channel region provided between the source and drain regions;

a gate insulating film formed on the semiconductor region; and

a gate electrode formed on the gate insulating film,

wherein a boundary between the source and the channel regions is located below said gate electrode while a boundary between the channel and the drain regions is outwardly offset from said gate electrode.

18. A semiconductor device comprising;

a semiconductor region formed over an insulating substrate;

a pair of impurity regions formed in the semiconductor region;

a channel region provided between the pair of impurity regions;

a gate insulating film on the semiconductor region; and

a gate electrode formed on the gate insulating film;

wherein a boundary between one of the impurity regions and the channel region is located below said gate electrode while a boundary between the other one of the impurity regions and the channel region is outwardly offset from said gate electrode.