Single piece package for semiconductor die

• US 5,739,585 A
• Filed: 07/29/1996
• Issued: 04/14/1998
• Est. Priority Date: 11/27/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Wood, Alan G., Farnworth, Warren M.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/688,060
• Time in Patent Office: 624 Days
• Field of Search: 257/698, 257/737, 257/738, 257/772, 257/787, 257/788, 257/673, 257/679, 257/680, 257/693, 257/750, 257/774, 257/775, 257/779
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1624 the bump connector connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49883 the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49133 : with component orienting

Abstract

A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.

Claims

1. A semiconductor package comprising:

a silicon package body, said package body comprising a first surface and a second surface, said second surface including a die mounting cavity;

an opening in the package body, said opening extending from the first surface to the die mounting cavity;

an electrically insulating layer formed on the first surface;

a pattern of conductors formed on the insulating layer, said conductors comprising a metal layer having a thickness of from 500 Å

to 10 μ

m;

a semiconductor die comprising a plurality of bond pads thereon, said die placed on the die mounting cavity with the bond pads aligned with the opening; and

a plurality of electrical interconnections extending through the opening to place the bond pads and conductors in electrical communication.

2. The package as claimed in claim 1 wherein the die mounting cavity includes sidewalls configured to align the bond pads with opening.

3. The package as claimed in claim 1 wherein the insulating layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, and polyimide.

4. The package as claimed in claim 1 further comprising a groove on the first surface wherein at least one conductor is located.

5. The package as claimed in claim 1 further comprising a curable material deposited within the cavity for encapsulating the die.

6. The package as claimed in claim 1 further comprising a curable material deposited within the opening for encapsulating the electrical interconnections.

7. The package as claimed in claim 1 further comprising a second cavity formed on the first surface and a lid attached to the second cavity to cover the electrical interconnections.

8. The package as claimed in claim 1 wherein the electrical interconnections comprise bonded wires.

9. The package as claimed in claim 1 wherein the bond pads comprise solder bumps and the electrical interconnections comprise reflowed solder.

10. A semiconductor package comprising:

a silicon package body comprising a first surface and an opposed second surface, said second surface including a plurality of grooves;

a plurality of conductors within the grooves;

an opening formed through the package body, said opening extending from the first surface to the second surface; and

a semiconductor die comprising a plurality of solder bumps thereon, said die placed on the first surface with the solder bumps reflowed into electrical communication with the conductors.

11. The package as claimed in claim 10 wherein the first surface includes a cavity with sidewalls configured to contact the die to align the solder bumps to the opening.

12. The package as claimed in claim 10 further comprising a plurality of dice placed on the first surface with solder bumps on the dice flowed into electrical communication with the conductors.

13. The package body as claimed in claim 10 further comprising an electrical insulating layer formed on the second surface and within the opening.

14. The package as claimed in claim 13 wherein the insulating layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride and polyimide.

15. The package as claimed in claim 10 wherein the pattern of conductors comprises a metallization layer having a thickness of from 500 Å

to 10 μ

m.

16. A semiconductor package comprising:

a silicon package body including a first surface and a second surface, said first surface including a first cavity, said second surface including a second cavity;

an opening formed through the package body from the first cavity to the second cavity;

a semiconductor die including a plurality of bond pads, said die attached to the first cavity with the bond pads aligned with the opening;

a pattern of conductors formed on the second surface of the package body and extending into the second cavity;

a plurality of wires extending through the opening in the package body, said wires bonded to the bond pads and to the conductors; and

a lid attached to the second surface covering the second cavity.

17. The package as claimed in claim 16 wherein the first cavity includes a curable material encapsulating the die.

18. The package as claimed in claim 16 further comprising a metal bump formed on at least one of the conductors.

19. The package as claimed in claim 18 further comprising a groove etched into the body wherein the metal bump is located.

20. The package as claimed in claim 16 further comprising a curable material deposited in the second cavity to encapsulate the wires.

21. The package as claimed in claim 16 wherein a plurality of dice are mounted to the first cavity.

22. The package as claimed in claim 16 wherein each conductor includes an insulating layer and a metal bump formed through a via in the insulating layer.

23. The package as claimed in claim 22 wherein the metal bumps comprise solder.

24. The package as claimed in claim 23 further comprising a barrier layer and a seed layer formed between the metal bumps and the conductors.

25. A semiconductor package comprising:

a package body comprising a resin-glass laminate with an elongated opening there through, said body including a first surface and an opposed second surface;

a semiconductor die comprising a circuit side with a plurality of bond pads, said circuit side attached to the first surface with an adhesive layer therebetween, and with the bond pads on the die in alignment with the opening;

a pattern of conductors formed on the second surface of the package body, at least one of said conductors including a metal ball;

a plurality of wires placed through the opening and bonded to the bond pads and conductors; and

a curable material placed within the opening to encapsulate at least a portion of the wires.

26. The package as claimed in claim 25 wherein the curable material comprises a material selected from the group consisting of epoxy, silicone, polyimide, and a room temperature vulcanizing material.

27. The package as claimed in claim 25 further comprising a solder mask formed on the conductors for attaching a plurality of solder bumps to the conductors.

28. The package as claimed in claim 25 further comprising an encapsulating material encapsulating the die.

29. The package as claimed in claim 25 wherein the resin-glass laminate comprises a FR-4 material.

30. The package as claimed in claim 25 wherein a plurality of dice are mounted to the first surface to form a multi chip module.