Semiconductor device

• US 5,739,588 A
• Filed: 04/05/1996
• Issued: 04/14/1998
• Est. Priority Date: 08/15/1994
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Inventors: Terashima, Kazuhiko, Toyoda, Takeshi, Ikeda, Ienobu, Ohmori, Yoshinobu, Ishida, Yoshihiro
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US08/624,496
• Time in Patent Office: 739 Days
• Field of Search: 257/700, 257/701, 257/702, 257/782, 257/774, 257/784, 361/777, 361/808, 361/809, 361/820
• US Class Current: 257/782
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15182 : Fan-in arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

In a semiconductor device comprising an IC chip (8) mounted on a circuit substrate (7) and sealed with a molding resin (11), corner resist films (6a, 6b, 6c, 6d) are formed at positions corresponding to a corner A of the IC chip (8) on the circuit substrate (7), and the corner A of the IC chip (8) is bonded to these corner resist films by using a die bond (9). A die pattern (3a) is exposed outside the corner resist films, and a power supply pattern (3b) is so formed to encompass their periphery. The power supply terminal, the die pattern (3a) and the power supply pattern (3b) are connected to the IC chip (8) of the corners of the IC chip is improved and peel is prevented. Furthermore, bonding of a large number of bonding wires for supplying power can be freely made.

Claims

1. A semiconductor device comprising:

a resin substrate,

an IC chip to be disposed on the resin substrate and having an outer bottom shape with corner portions and a plurality of electrodes,

a circuit substrate mounted on the resin substrate, said circuit substrate including a die pattern for securing the IC chip onto the resin substrate, said die pattern having an outer shape greater than the outer bottom shape of the IC chip, and a connecting electrode for connecting the electrodes of the IC chip,

an insulating film having an outer shape smaller than that of the die pattern, said insulating film being disposed on the die pattern at a portion at least corresponding to the corner portions of the IC chip, said IC chip being die bonded to the insulating film, and

bonding wires connected between the IC chip and a part of the die pattern exposed from the insulating film.

2. A semiconductor device as claimed in claim 1, wherein said bonding wires supply power to the IC chip.

3. A semiconductor device as claimed in claim 1, wherein said corners of the IC chip are located inside the insulating film.

4. A semiconductor device as claimed in claim 1, wherein said die pattern has a center area and outer areas without being covered by the insulating film, said center and outer areas having gold plating thereon.

5. A semiconductor device as claimed in claim 1, wherein said die pattern comprises:

a main pattern formed in a center area of a position at which the IC chip is mounted, bonding patterns formed outside of the position at which the IC chip is mounted, and combination patterns electrically connecting the main pattern and the bonding patterns; and

said insulating film is situated between the main pattern and the bonding pattern.

6. A semiconductor device as claimed in claim 5, wherein said bonding patterns are positioned outside four sides of the main pattern to surround the main pattern;

and said combination patterns are arranged radially from the main pattern to the bonding patterns.

7. A semiconductor device as claimed in claim 6, wherein said combination patterns are arranged at a section outside of the corner portions of the IC chip.

8. A semiconductor device as claimed in claim 6, wherein said insulating film is formed in a circular shape for substantially covering the region at which the combination patterns are formed.

9. A semiconductor device as claimed in claim 6, wherein said insulating film is formed so as to cover a section corresponding to the corner portions of the IC chip in the region at which the combination patterns are formed.

10. A semiconductor device as claimed in claim 5, wherein said insulating film is attached so that one part of the main pattern is exposed therefrom.

11. A semiconductor device as claimed in claim 5, wherein said insulating film is a plating resist and gold plating is applied on the die pattern which is not covered with the plating resist.

12. A semiconductor device as claimed in claim 11 wherein said plating resist is a developing-type liquid solder resist.