Digitally controlled oscillator circuit

• US 5,739,725 A
• Filed: 01/29/1996
• Issued: 04/14/1998
• Est. Priority Date: 01/29/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Masenas, Charles Joseph Jr., Ferraiolo, Frank David, Gersbach, John Edwin
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/593,754
• Time in Patent Office: 806 Days
• Field of Search: 331/57, 331/10, 331/17, 331/34
• US Class Current: 331/57
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A variable frequency oscillator circuit includes a ring oscillator circuit, a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit, at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching.

Claims

1. An oscillator circuit, comprising:

a phase comparator having first and second clock signal inputs, and outputs having predetermined relationships to characteristics of the first and second clock signals;

a ring oscillator circuit;

a first control means connected to a first output of the phase comparator for generating a first control current, the first control current having a value within a first range of control currents, the first control current being supplied to the ring oscillator, resulting in the adjustment of an output frequency of the ring oscillator circuit over a first frequency adjustment range, the first control means also providing as an output a first set of digital signals;

a second control means connected to an output of the first control means for generating a second control current, the second control current having a value within a second range of control currents, the second control current being supplied to the ring oscillator circuit, resulting in adjustment of the output frequency of the ring oscillator circuit over a second frequency adjustment range.

2. An oscillator circuit, according to claim 1, wherein:

the second control current is generated at a predetermined rate which is lower than the rate of generation of the first control current.

3. An oscillator circuit, according to claim 2, wherein:

generation of the second control current is initiated while the first control current is within the first range of control currents.

4. An oscillator circuit, according to claim 1, further comprising:

a feedback circuit, having an input responsive to an output of the ring oscillator and an output connected to an input of the phase comparator, the feedback circuit controlled by a digital signal.

5. An oscillator circuit, according to claim 1, wherein the first control means further comprises:

a first counter providing output signals at a first resolution.

6. An oscillator circuit, according to claim 1, wherein the second control means further comprises:

a second counter providing output signals at a second resolution.

7. A semiconductor integrated circuit, comprising:

a phase comparator having first and second clock signal inputs, and outputs having predetermined relationships to characteristics of the first and second clock signals;

a ring oscillator circuit;

a first control means connected to the output of the phase comparator for generating a first control current, the first control current having a value within a first range of control currents, the first control current being supplied to the ring oscillator, resulting in the adjustment of an output frequency of the ring oscillator circuit over a first frequency adjustment range, the first control means also providing as an output a first set of digital signals;

a second control means connected to an output of the first control means for generating a second control current, the second control current having a value within a second range of control currents, the second control current being supplied to the ring oscillator circuit, resulting in adjustment of the output frequency of the ring oscillator circuit over a second frequency adjustment range.

8. A semiconductor integrated circuit, according to claim 7, wherein:

the second control current is generated at a predetermined rate which is lower than the rate of generation of the first control current.

9. A semiconductor integrated circuit, according to claim 8, wherein:

generation of the second control current is initiated while the first control current is within the first range of control currents.

10. A semiconductor integrated circuit, according to claim 7, further comprising:

a feedback circuit, having an input responsive to an output of the ring oscillator and an output connected to an input of the phase comparator, the feedback circuit controlled by a digital signal.

11. A semiconductor integrated circuit, according to claim 7, wherein the first control means further comprises:

a first counter providing output signals at a first resolution.

12. A semiconductor integrated circuit, according to claim 7, wherein the second control means further comprises:

a second counter providing output signals at a second resolution.

13. A digitally controlled oscillator circuit, comprising:

a ring oscillator circuit;

a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit;

at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching, wherein the plurality of adjustment means further comprises;

first and a second control circuits, the first control circuit generating a first control current, the first control current having a value within a first range of control currents, the first control current being supplied to the ring oscillator, resulting in the adjustment of an output frequency of the ring oscillator circuit over a first frequently adjustment range, the first control means also providing as an output a first set of digital signals;

a second control means connected to an output of the first control means for generating a second control current, the second control current having a value within a second range of control currents, the second control current being supplied to the ring oscillator circuit, resulting in adjustment of the output frequency of the ring oscillator circuit over a second frequency adjustment range.

14. A digitally controlled oscillator circuit, according to claim 13, wherein:

generation of the second control current is initiated while the first control current is within the first range of control currents.

15. A digitally controlled oscillator circuit, according to claim 13, wherein the first control means further comprises:

a first counter providing output signals at a first resolution.

16. A digitally controlled oscillator circuit, according to claim 13, wherein the second control means further comprises:

a second counter providing output signals at a second resolution.