Sub-ranging analog-to-digital converter with open-loop differential amplifiers

• US 5,739,781 A
• Filed: 10/08/1996
• Issued: 04/14/1998
• Est. Priority Date: 10/08/1996
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kagey, Mark R.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): VICK, JASON
• Application Number:
  US08/727,056
• Time in Patent Office: 553 Days
• Field of Search: 341/155, 341/139, 341/158, 341/159
• US Class Current: 341/155
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A sub-ranging analog to digital converter utilizes open loop differential gain amplifiers and analog switches to implement a pipeline. Each stage of the converter contains two fine range transfer amplifiers, sampling switches and hold capacitors, a low resolution sub-range analog to digital converter and a resistive ladder. The sampling switches behave as a digital to analog converter. Each stage then converts the held analog value to a digital code, which is used to operate the transfer switches to select the proper sub-range result for the next stage. The transfer switches are analog switches that perform the function of both the sampling and the sub-range transfer. The interstage amplifiers are simple open loop differential amplifiers with a rather imprecise absolute gain. Because the reference and the signal are both amplified by this imprecise gain, both the reference and the signal are amplified by the same amount. A preprocessing circuit transforms a single ended input to the analog to digital converter into four separate signals which, taken together, represent the input and reference information. Since the fine range transfer amplifiers are differential amplifiers they reject the common mode that might occur from stage to stage. However the fine range transfer amplifiers restore the signal to approximately the same common mode level at the input to each stage. Embodiments producing single or multiple output bits per stage with synchronous stages using either sub-range signal sample and hold amplifiers or dual purpose subrange transfer and sampling switches are disclosed.

Claims

1. An apparatus including an analog-to-digital converter (ADC) stage for use in a subranging ADC system, said ADC stage comprising:

a plurality of input amplifiers configured to receive and amplify a plurality of analog input signals and in accordance therewith provide first, second, third and fourth amplified analog signals, wherein said first amplified analog signal has a first amplified voltage, said second amplified analog signal is an inverse of said first amplified analog signal and has a second amplified voltage, said third amplified analog signal has a third amplified voltage which differs from said first amplified voltage by a first voltage offset, and said fourth amplified analog signal has a fourth amplified voltage which differs from said second amplified voltage by a second voltage offset;

a signal interpolation circuit, coupled to said plurality of input amplifiers, configured to receive and interpolate said first and third amplified analog signals and receive and interpolate said second and fourth amplified analog signals and in accordance therewith provide a plurality of analog interpolation signals; and

a signal comparison circuit, coupled to said signal interpolation circuit, configured to receive and compare individual ones of said plurality of analog interpolation signals and in accordance therewith provide one or more digital signals, wherein each one of said one or more digital signals includes asserted and de-asserted states.

2. The apparatus of claim 1, wherein:

said plurality of analog input signals comprises

a first analog input signal which has a first input voltage,

a second analog input signal which is an inverse of said first analog input signal and has a second input voltage,

a third analog input signal having a third input voltage which differs from said first input voltage by said first voltage offset, and

a fourth analog input signal having a fourth input voltage which differs from said second input voltage by said second voltage offset; and

said plurality of input amplifiers comprises

a first differential amplifier configured to differentially receive and amplify said first and fourth analog input signals and in accordance therewith provide said first and fourth amplified analog signals, and

a second differential amplifier configured to differentially receive and amplify said second and third analog input signals and in accordance therewith provide said second and third amplified analog signals.

3. The apparatus of claim 1, wherein said signal interpolation circuit comprises a voltage divider circuit configured to differentially receive and divide said first and third amplified voltages and differentially receive and divide said second and fourth amplified voltages.

4. The apparatus of claim 1, wherein said signal comparison circuit comprises one or more voltage comparators, each one of which is configured to receive and compare a pair of individual ones of said plurality of analog interpolation signals and in accordance therewith provide one or more of said one or more digital signals.

5. The apparatus of claim 1, wherein said signal comparison circuit comprises:

a plurality of voltage comparators configured to receive and compare pairs of individual ones of said plurality of analog interpolation signals and in accordance therewith provide a plurality of logic signals; and

a logic circuit, coupled to said plurality of voltage comparators, configured to receive and logically process said plurality of logic signals and in accordance therewith provide said one or more digital signals.

6. The apparatus of claim 1, further comprising a signal selection circuit, coupled to said signal interpolation circuit and said signal comparison circuit, configured to receive said one or more digital signals and in accordance therewith receive and select among said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals and in accordance therewith provide first, second, third and fourth analog output signals which include a pair of said plurality of analog interpolation signals.

7. The apparatus of claim 6, wherein said signal selection circuit comprises a plurality of switches, each one of which is configured to receive one of said one or more digital signals and to receive one of said first, second, third and fourth amplified analog signals or one of said plurality of analog interpolation signals and to close and open in accordance with said asserted and de-asserted states of a respective one of said one or more digital signals.

8. The apparatus of claim 6, wherein:

said signal selection circuit is configured to sample selected ones of said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals in accordance with said one or more digital signals and in accordance therewith provide first, second, third and fourth signal samples as said first, second, third and fourth analog output signals; and

said ADC stage further comprises an output signal holding circuit, coupled to said signal selection circuit, configured to hold said first, second, third and fourth signal samples.

9. The apparatus of claim 8, wherein said output signal holding circuit comprises a plurality of capacitors.

10. The apparatus of claim 1, further comprising a preprocessing circuit, coupled to said plurality of input amplifiers, configured to receive said first and second analog input signals, generate said first and second voltage offsets and in accordance therewith provide said third and fourth analog input signals.

11. The apparatus of claim 10, further comprising a converter circuit, coupled to said preprocessing circuit, configured to receive and convert a single ended analog signal to a differential analog signal which forms said first and second analog input signals.

12. An apparatus including a subranging analog-to-digital converter (ADC) system comprising:

a plurality of ADC stages, each one of which includes

a plurality of input amplifiers configured to receive and amplify a plurality of analog input signals and in accordance therewith provide first, second, third and fourth amplified analog signals, wherein said first amplified analog signal has a first amplified voltage, said second amplified analog signal is an inverse of said first amplified analog signal and has a second amplified voltage, said third amplified analog signal has a third amplified voltage which differs from said first amplified voltage by a first voltage offset, and said fourth amplified analog signal has a fourth amplified voltage which differs from said second amplified voltage by a second voltage offset, and

a signal interpolation circuit, coupled to said plurality of input amplifiers, configured to receive and interpolate said first and third amplified analog signals and receive and interpolate said second and fourth amplified analog signals and in accordance therewith provide a plurality of analog interpolation signals; and

a plurality of signal selection circuits, each one of which is coupled between an upstream ADC stage and a downstream ADC stage of said plurality of ADC stages and is configured to receive from said upstream ADC stage said one or more digital signals and in accordance therewith receive from said upstream ADC stage and select among said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals and in accordance therewith provide to said downstream ADC stage first, second, third and fourth analog output signals which include a pair of said plurality of analog interpolation signals.

13. The apparatus of claim 12, wherein:

said plurality of analog input signals comprises

a first analog input signal which has a first input voltage,

a second analog input signal which is an inverse of said first analog input signal and has a second input voltage,

a third analog input signal having a third input voltage which differs from said first input voltage by said first voltage offset, and

a fourth analog input signal having a fourth input voltage which differs from said second input voltage by said second voltage offset; and

each one of said plurality of input amplifiers comprises

a first differential amplifier configured to differentially receive and amplify said first and fourth analog input signals and in accordance therewith provide said first and fourth amplified analog signals, and

a second differential amplifier configured to differentially receive and amplify said second and third analog input signals and in accordance therewith provide said second and third amplified analog signals.

14. The apparatus of claim 12, wherein said signal interpolation circuit comprises a voltage divider circuit configured to differentially receive and divide said first and third amplified voltages and differentially receive and divide said second and fourth amplified voltages.

15. The apparatus of claim 12, wherein said signal comparison circuit comprises one or more voltage comparators, each one of which is configured to receive and compare a pair of individual ones of said plurality of analog interpolation signals and in accordance therewith provide one or more of said one or more digital signals.

16. The apparatus of claim 12, wherein said signal comparison circuit comprises:

a plurality of voltage comparators configured to receive and compare pairs of individual ones of said plurality of analog interpolation signals and in accordance therewith provide a plurality of logic signals; and

a logic circuit, coupled to said plurality of voltage comparators, configured to receive and logically process said plurality of logic signals and in accordance therewith provide said one or more digital signals.

17. The apparatus of claim 12, wherein each one of said plurality of signal selection circuits comprises a plurality of switches, each one of which is configured to receive one of said one or more digital signals and to receive one of said first, second, third and fourth amplified analog signals or one of said plurality of analog interpolation signals and to close and open in accordance with said asserted and de-asserted states of a respective one of said one or more digital signals.

18. The apparatus of claim 12, wherein:

each one of said plurality of signal selection circuits is configured to sample selected ones of said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals in accordance with said one or more digital signals and in accordance therewith provide first, second, third and fourth signal samples as said first, second, third and fourth analog output signals; and

said subranging ADC system further comprises a plurality of output signal holding circuits, each one of which is coupled between a respective one of said plurality of signal selection circuits and said downstream ADC stage and is configured to hold said first, second, third and fourth signal samples.

19. The apparatus of claim 18, wherein each one of said plurality of output signal holding circuits comprises a plurality of capacitors.

20. The apparatus of claim 12, further comprising a preprocessing circuit, coupled to a first one of said plurality of ADC stages, configured to receive said first and second analog input signals, generate said first and second voltage offsets and in accordance therewith provide said third and fourth analog input signals.

21. The apparatus of claim 20, further comprising a converter circuit, coupled to said preprocessing circuit, configured to receive and convert a single ended analog signal to a differential analog signal which forms said first and second analog input signals.

22. The apparatus of claim 12, further comprising a plurality of latch circuits, each one of which is coupled to a respective selected one of said signal comparison circuits and is configured to receive and latch one of said one or more digital signals.

23. The apparatus of claim 12, further comprising an addressable storage circuit, coupled to said signal comparison circuits, configured to receive said digital signals and in accordance therewith provide a plurality of digital data.

24. A method of performing a subranging analog-to-digital signal conversion comprising the steps of:

receiving and amplifying a plurality of analog input signals and in accordance therewith generating first, second, third and fourth amplified analog signals, wherein said first amplified analog signal has a first amplified voltage, said second amplified analog signal is an inverse of said first amplified analog signal and has a second amplified voltage, said third amplified analog signal has a third amplified voltage which differs from said first amplified voltage by a first voltage offset, and said fourth amplified analog signal has a fourth amplified voltage which differs from said second amplified voltage by a second voltage offset;

interpolating said first and third amplified analog signals and interpolating said second and fourth amplified analog signals and in accordance therewith generating a plurality of analog interpolation signals; and

comparing individual ones of said plurality of analog interpolation signals and in accordance therewith generating one or more digital signals, wherein each one of said one or more digital signals includes asserted and de-asserted states.

25. The method of claim 24, wherein:

said plurality of analog input signals comprises

a first analog input signal which has a first input voltage,

a second analog input signal which is an inverse of said first analog input signal and has a second input voltage,

a third analog input signal having a third input voltage which differs from said first input voltage by said first voltage offset, and

a fourth analog input signal having a fourth input voltage which differs from said second input voltage by said second voltage offset; and

said step of receiving and amplifying a plurality of analog input signals and in accordance therewith generating first, second, third and fourth amplified analog signals comprises

differentially receiving and amplifying said first and fourth analog input signals and in accordance therewith generating said first and fourth amplified analog signals, and

differentially receiving and amplifying said second and third analog input signals and in accordance therewith generating said second and third amplified analog signals.

26. The method of claim 24, wherein said step of interpolating said first and third amplified analog signals and interpolating said second and fourth amplified analog signals and in accordance therewith generating a plurality of analog interpolation signals comprises differentially receiving and voltage dividing said first and third amplified voltages and differentially receiving and voltage dividing said second and fourth amplified voltages.

27. The method of claim 24, wherein said step of comparing individual ones of said plurality of analog interpolation signals and in accordance therewith generating one or more digital signals comprises:

comparing pairs of individual ones of said plurality of analog interpolation signals and in accordance therewith generating a plurality of logic signals; and

logically processing said plurality of logic signals and in accordance therewith generating said one or more digital signals.

28. The method of claim 24, further comprising the step of selecting, in accordance with said one or more digital signals, among said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals and in accordance therewith generating first, second, third and fourth analog output signals which include a pair of said plurality of analog interpolation signals.

29. The method of claim 28, wherein:

said step of selecting, in accordance with said one or more digital signals, among said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals and in accordance therewith generating first, second, third and fourth analog output signals comprises sampling selected ones of said first, second, third and fourth amplified analog signals and said plurality of analog interpolation signals in accordance with said one or more digital signals and in accordance therewith generating first, second, third and fourth signal samples as said first, second, third and fourth analog output signals; and

further comprising the step of holding said first, second, third and fourth signal samples.

30. The method of claim 29, wherein said step of holding said first, second, third and fourth signal samples comprises selectively charging a plurality of capacitors.

31. The method of claim 24, further comprising the steps of receiving said first and second analog input signals, generating said first and second voltage offsets and in accordance therewith generating said third and fourth analog input signals.

32. The method of claim 31, further comprising the step of receiving and convening a single ended analog signal to a differential analog signal which forms said first and second analog input signals.

33. The method of claim 24, further comprising the step of latching one of said one or more digital signals.

34. The method of claim 24, further comprising the step of addressing an addressable storage circuit with said digital signals and in accordance therewith generating a plurality of digital data.