Scalable multimedia network

• US 5,740,176 A
• Filed: 04/29/1996
• Issued: 04/14/1998
• Est. Priority Date: 05/19/1994
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: DAGAZ Technologies, Inc. (Cisco Systems, Inc.)
• Inventors: Gupta, Dev Vrat, Stone, Alan E., Sharper, Craig A., Chen, Yu-Ren Brian
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/638,761
• Time in Patent Office: 715 Days
• Field of Search: 370/449, 370/450, 370/451, 370/455, 370/463, 370/465, 370/471, 370/474, 370/489, 370/438, 370/439, 370/440, 370/412, 370/389, 370/392, 370/395, 370/400, 370/401, 370/402, 340/825.51, 340/825.52, 340/825.5
• US Class Current: 370/440
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 12/2852 Metropolitan area networks
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5612 Ring
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/6427 Subscriber Access Module; Concentrator; Group equipment
• CPC Class Codes: H04L 2012/6443 Network Node Interface, e.g. Routing, Path finding
• CPC Class Codes: H04L 2012/6448 Medium Access Control [MAC]
• CPC Class Codes: H04L 2012/6459 Multiplexing, e.g. TDMA, CDMA
• CPC Class Codes: H04L 2012/6464 Priority
• CPC Class Codes: H04L 2012/6483 Video, e.g. MPEG
• CPC Class Codes: H04L 2012/6486 Signalling Protocols
• CPC Class Codes: H04L 2012/6489 : Buffer Management, Threshold setting, Scheduling, Shaping
• CPC Class Codes: H04L 49/107 : using shared medium
• CPC Class Codes: H04L 65/1026 : at the edge
• CPC Class Codes: H04L 65/1036 : at the edge
• CPC Class Codes: H04L 65/1101 : Session protocols
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 9/40 : Network security protocols
• CPC Class Codes: H04N 21/6118 : involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 21/64707 : for transferring content from a first network to a second network, e.g. between IP and wireless
• CPC Class Codes: H04N 7/173 : with two-way working, e.g. subscriber sending a programme selection signal
• CPC Class Codes: H04N 7/17309 : Transmission or handling of upstream communications
• CPC Class Codes: H04N 7/17336 : Handling of requests in head-ends
• CPC Class Codes: H04N 7/17345 : Control of the passage of the selected programme
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections

Abstract

A Scalable Multimedia Network providing integrated networking of data, voice, video and image services over a variety of access facilities including metallic loops, fiber/coax or digital fiber is disclosed herein.

The SMN establishes customer initiated switched virtual circuits for all traffic types and directs them to the appropriate backbone network. The SMN is based on a distributed switching platform that enables carriers to economically provide service to a small number of customers and add capacity incrementally as the customer base increases. The platform has a protocol adaptation capability which permits communications between customer premises equipment and potentially incompatible backbone networks or network servers.

Claims

1. In a communication system comprising first and second uni-directional buses oppositely directed, a plurality of units, each said unit and at least one end unit coupled to both buses, said at least one end unit for generating cells on said first bus, said cells including request, idle, empty, and payload cells, at least another end unit for connecting said first bus to said second bus, a method for controlling transmission of said cells, including the steps of:

generating at said at least one end unit a cell pattern comprising a series consisting of a request cell of first priority followed by N empty cells of first priority, said series repeating x times and y idle cells;

transmitting said cell pattern at said at least one end unit onto said first bus;

receiving said cell pattern at one of said units on said first bus;

modifying said request cell at said one unit in response to at least one packet having been collected in a priority queue in said unit;

transmitting said modified request cell at said one unit onto said first bus;

receiving said request cell at said at least one end unit on said second bus and modifying a priority counter in response to a logical value of said request cell;

generating said empty cells at said at least one end unit onto said first bus in response to a logical value of said priority counter.

5. The method of claim 1 wherein N=64, X=24, and Y=2.5.

6. The method of claim 1 further comprising decrementing said priority counter for each generated empty cell.

7. The method of claim 6 further comprising generating an empty cell of second priority at said one end unit onto said first bus in response to said priority counter reaching zero.

2. Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising:

a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal into a first N bit parallel signal;

a first register for retiming said first N bit parallel signal;

a detector circuit responsive to the output of said first register for detecting said empty cells;

a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells;

an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit;

an arbiter multiplexer circuit for selecting among said first N bit parallel signal from said first register, said request cell modified by said adder circuit, and said payload cells from said first controller circuit,

a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first M bit parallel signal and for converting said first M bit parallel signal into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus;

a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal into a second N bit parallel signal;

a second register for retiming said second N bit parallel signal;

a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and

a second encoder circuit for encoding said second N bit parallel signal into a second M bit parallel signal and for converting said second M bit parallel signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

3. The apparatus of claim 2 further comprising:

a cell scheduler circuit for examining said cells contained in said second N bit parallel signal such that a count contained in each said request cell is maintained, a number of said empty cells responsive to said count are generated, and said request cell is generated following said generated empty cells.

4. The apparatus of claim 2 wherein N=32 and M=20.

8. In a communication system comprising first and second buses, a plurality of units, each said unit and an end unit coupled to both buses, said end unit for generating cells on said first bus, said cells including request, idle, empty, and payload cells, a method for controlling transmission of said cells, including the steps of:

generating at said end unit a cell pattern;

transmitting said cell pattern at said end unit onto said first bus;

modifying said cell pattern at one of said units in response to at least one packet having been collected in a priority queue in said one unit;

transmitting said modified cell pattern at said one unit onto said first bus; and

receiving said modified cell pattern at said end unit on said second bus and modifying a priority counter in response to a logical value of said cell pattern.

9. The method of claim 8 wherein the cell pattern comprises a series consisting of a request cell of first priority followed by N empty cells of first priority, said series repeating x times and y idle cells.

10. The method of claim 9 further comprising generating said empty cells at said end unit onto said first bus in response to a logical value of said priority counter.

11. The method of claim 9 wherein N=64, X=24, and Y=2.5.

12. The method of claim 10 further comprising decrementing said priority counter for each generated empty cell.

13. The method of claim 12 further comprising generating an empty cell of second priority at said end unit onto said first bus in response to said priority counter reaching zero.

14. Apparatus for interconnecting a first bus and a second bus having an upward path and a downward path, wherein said buses carry data formatted into cells, wherein said cells comprise request empty, payload and idle cells, comprising:

a first decoder circuit for receiving a first serial input signal from said upward path of said second bus and for decoding said first serial input signal;

a detector circuit coupled to said first decoder circuit for detecting said empty cells;

a first controller circuit for receiving packet data from said first bus and for writing said packet data into said empty cells, whereby said empty cells are transformed into said payload cells;

an adder circuit for modifying said request cell in response to at least one packet having been collected in said first controller circuit;

an arbiter multiplexer circuit for selecting among said first decoded serial input signal, said request cell modified by said adder circuit, and said payload cells from said first controller circuit;

a first encoder circuit for encoding an output of said arbiter multiplexer circuit into a first serial output signal and for transmitting said first serial output signal to said upward path of said second bus;

a second decoder circuit for receiving a second serial input signal from said downward path of said second bus and for decoding said second serial input signal;

a second controller circuit for extracting said packet data from said payload cells and for transmitting said extracted packet data to said first bus; and

a second encoder circuit for encoding said second serial input signal into a second serial output signal and for transmitting said second serial output signal to said downward path of said second bus.

15. The apparatus of claim 14 further comprising:

a cell scheduler circuit for examining said cells contained in said second serial input signal such that a count contained in each said request cell is maintained, a number of said empty cells responsive to said count are generated, and said request cell is generated following said generated empty cells.