Reconfigurable computer system

• US 5,740,350 A
• Filed: 03/18/1997
• Issued: 04/14/1998
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: McCaslin, Clark D., Rabins, Leonard, Selway, David W., Kesner, Donald R., Bowman, David A.
• Primary Examiner(s): Decady, Albert
• Application Number:
  US08/823,663
• Time in Patent Office: 392 Days
• Field of Search: 395/180, 395/181, 395/182.01, 395/182.08, 395/182.09, 395/182.1, 395/185.01, 395/651, 395/653, 395/800, 395/182.11, 364/229.4
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.

Claims

1. In a reconfigurable computer system including:

a first and a second computer subsystem;

each computer subsystem including a system control unit (SCU), at least one central processing unit (CPU), at least one input output processor unit (IOPU), a plurality of memory units (MU)s, a power supply unit (PSU), a clock and maintenance unit (CMU), a service processor (SP), a system bus (SB), the SB including data lines, address lines, command lines, and control lines;

a memory bus (MB), a clock and maintenance bus (CMB), a power supply bus (PSB), and a local area network bus (LANB);

error detection circuit means incorporated in each unit for detecting errors and producing error signals identifying each error detected;

the SCU interconnecting and controlling the system bus and memory bus, the CPUs and IOPUs being connected to the SB, MUs being connected to the MB, the CMU being connected to each of the units of a subsystem by the CMB, the PSU being connected to each of the units of a subsystem by the PSB, and the SP being connected to the CMU by the LANB;

the CMU receiving error signals produced by said error detection circuits of the units of a subsystem, said error signals being transmitted to the SP via the LANB, the SP being programmed to analyze errors reported by the units of a subsystem and to initiate appropriate corrective action via the CMU and CMB, the SP upon the occurrence of a single point failure that will render a subsystem inoperative, shutting down the subsystem;

wherein the improvements comprise;

incorporating additional control lines in the SBs of the two computer subsystems;

switch means having a closed state and an open state, said switch means in its closed state electrically connecting corresponding lines of each SB to merge the two subsystems into a single computer system, said switch means in its open state electrically isolating said lines;

the additional control lines of the SBs when the switch means are closed and the subsystems merged permitting the SCUs of the first and second computer subsystem to communicate with each other, the SCU of one of the two subsystems controlling access to the SBs of both subsystems by the units connected to said SBs, the SCU in control;

the SCU of the other subsystem following the lead of the SCU in control when the two subsystems are merged;

the switch means when open electrically isolating the lines of the SB of the first computer subsystem from the lines of the second computer subsystem to reconfigure the computer system so that each computer subsystem can function independently;

repeater circuit means for connecting the LANBs of the two computer subsystem so that the SPs of the two subsystems receive information transmitted by the CMUs of either subsystem over the. LANBs and outputs produced by the other SP, such as that a SP has detected that a single point of failure has occurred in its subsystem and that said SP is shutting down its subsystem;

a repeater control bus (RCB) for connecting the CMU of each subsystem to the repeater circuit means, the CMUs of each subsystem controlling the operation of the repeater circuit means;

the SP of a subsystem detecting a single point failure having occurred in its subsystem causing the CMU of its subsystem to render the repeater circuit means inoperative and the switch means to open;

the SP of a subsystem learning that a single point of failure has occurred in the other subsystem causing the CMU of its sub-system to render the repeater circuit means inoperative and the switch means to open to reconfigure the computer system to isolate the two subsystems so that the subsystem that has not suffered a single point failure can continue to operate.

2. In the reconfigurable computer system of claim 1 in which switch the means includes a switch cell for each line of the SB of a computer subsystem, each switch cell comprising a first and a second CMOS switch connected in series;

each CMOS switch having two states, a first state in which the CMOS switch is open and a second state in which the CMOS switch is closed, the state of the first CMOS switch of each switch cell being determined by control circuit means of the CMU of the first computer subsystem, and the state of the second CMOS switch of each switch cell being determined by the control circuit means of the CMU of the second computer subsystem.