Instruction pointer limits in processor that performs speculative out-of-order instruction execution

• US 5,740,393 A
• Filed: 09/30/1996
• Issued: 04/14/1998
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vidwans, Rohit A., Glew, Andrew F., Boggs, Darrell D., Fetterman, Michael A.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Myers, Paul R.
• Application Number:
  US08/723,286
• Time in Patent Office: 561 Days
• Field of Search: 395/275, 395/376, 395/800, 395/391, 395/584, 395/586
• US Class Current: 712/215
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation. The retire circuit also determines whether each speculative instruction pointer exceeds the instruction pointer limit. The retire circuit commits the result data value of each instruction to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.

Claims

1. A method for enforcing an instruction pointer limit in an out-of-order processor, comprising the steps of:

reading a set of reorder buffer entries, the reorder buffer entries storing a set of result data values from out-of-order speculative execution of a set of instructions, wherein the reorder buffer entries comprise a first and a second reorder buffer entry, a first instruction corresponding to the first reorder buffer entry occurring before a second instruction corresponding to the second reorder buffer entry;

determining a speculative instruction pointer for each reorder buffer entry, wherein a first speculative instruction pointer for the first reorder buffer entry is determined by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry that indicates a length of the first instruction, and a second speculative instruction pointer for the second reorder buffer entry is determined by adding the instruction pointer to the instruction pointer delta value for the first instruction and an instruction pointer delta value from the second reorder buffer entry that indicates a length of the second instruction;

determining whether each speculative instruction pointer exceeds the instruction pointer limit; and

committing the result data value of each reorder buffer entry to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.

2. The method of claim 1, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

3. The method of claim 1, wherein the step of determining a speculative instruction pointer for each reorder buffer entry comprises the steps of:

determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry.

4. The method of claim 3, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

5. The method of claim 1, wherein the reorder buffer entries further comprise a third reorder buffer entry that occurs after the second reorder buffer entry in the sequential program order.

6. The method of claim 5, wherein the step of determining a speculative instruction pointer for each reorder buffer entry further comprises the step of:

determining a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, and an instruction pointer delta value from the third reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the third reorder buffer entry.

7. The method of claim 6, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

8. The method of claim 5, wherein the step of determining a speculative instruction pointer each reorder buffer entry comprises the steps of:

determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry.

9. The method of claim 8, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

10. The method of claim 5, wherein the reorder buffer entries further comprise a fourth reorder buffer entry that occurs after the third reorder buffer entry in the sequential program order.

11. The method of claim 10, wherein the step of determining a speculative instruction pointer each reorder buffer entry further comprises the steps of:

determining a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry; and

determining a speculative instruction pointer for the fourth reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the fourth reorder buffer entry, the instruction pointer delta value from the fourth reorder buffer entry indicating a length of the instruction corresponding to the fourth reorder buffer entry.

12. The method of claim 11, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the fourth reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

13. The method of claim 10, wherein the step of determining a speculative instruction pointer each reorder buffer entry comprises the steps of:

determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry;

determining a speculative instruction pointer for the fourth reorder buffer entry equal to a result data value from the fourth reorder buffer entry.

14. The method of claim 13, wherein the step of determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises the steps of:

determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

determining that the speculative instruction pointer for the fourth reorder buffer entry exceeds the instruction pointer limit if the result data value for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

15. A circuit for enforcing an instruction pointer limit in an out-of-order processor, comprising:

a circuit for reading a set of reorder buffer entries, the reorder buffer entries storing a set of result data values from out-of-order speculative execution of a set of instructions, wherein the reorder buffer entries comprise a first and a second reorder buffer entry, a first instruction corresponding to the first reorder buffer entry occurring before a second instruction corresponding to the second reorder buffer entry;

a circuit for determining a speculative instruction pointer for each reorder buffer entry, wherein a first speculative instruction pointer for the first reorder buffer entry is determined by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry that indicates a length of the first instruction, and a second speculative instruction pointer for the second reorder buffer entry is determined by adding the instruction pointer to the instruction pointer delta value for the first instruction and an instruction pointer delta value from the second reorder buffer entry that indicates a length of the second instruction;

a circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit; and

a circuit for committing the result data value of each reorder buffer entry to the architectural state if the speculative instruction pointer of the result data value does not exceed the instruction pointer limit.

16. The circuit of claim 15, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

17. The circuit of claim 15, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry.

18. The circuit of claim 17, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction limit plus one.

19. The circuit of claim 15, wherein the reorder buffer entries further comprise a third reorder buffer entry that occurs after the second reorder buffer entry in the sequential program order.

20. The circuit of claim 19, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry further comprises:

a circuit for determining a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, and an instruction pointer delta value from the third recorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the third reorder buffer entry.

21. The circuit of claim 20, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer of the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one; and

a circuit for determining tat the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

22. The circuit of claim 19, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

a circuit for determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry.

23. The circuit of claim 22, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

24. The circuit of claim 19, wherein the reorder buffer entries further comprise a fourth reorder buffer entry that occurs after the third reorder buffer entry in the sequential program order.

25. The circuit of claim 24, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry further comprises:

a circuit for determining a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry; and

a circuit for determining a speculative instruction pointer for the fourth reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the fourth reorder buffer entry, the instruction pointer delta value from the fourth reorder buffer entry indicating a length of the instruction corresponding to the fourth reorder buffer entry.

26. The circuit of claim 25, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the fourth reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

27. The circuit of claim 24, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

a circuit for determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry;

a circuit for determining a speculative instruction pointer for the fourth reorder buffer entry equal to a result data value from the fourth reorder buffer entry.

28. The circuit of claim 27, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the third reorder buffer entry exceeds the instruction pointer limit if the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the fourth reorder buffer entry exceeds the instruction pointer limit if the result data value for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

29. A circuit for enforcing an instruction pointer limit in an out-of-order processor, comprising:

a read control circuit reading a set of reorder buffer entries, the reorder buffer entries storing a set of result data values from out-of-order speculative execution of a set of instructions, wherein the reorder buffer entries comprise a first and a second reorder buffer entry, a first instruction corresponding to the first reorder buffer entry occurring before a second instruction corresponding to the second reorder buffer entry;

an instruction pointer logic circuit determining a speculative instruction pointer for each reorder buffer entry, comprising;

a first adder circuit generating a speculative instruction pointer for the first reorder buffer entry by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the first reorder buffer entry indicates a length of the instruction corresponding to the first reorder buffer entry, and

a second adder circuit a speculative instruction pointer for the second reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry,

the instruction pointer logic circuit determining whether each speculative instruction pointer exceeds the instruction pointer limit;

an event circuit committing the result data value of each reorder buffer entry to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.

30. The circuit of claim 29, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a second comparator circuit determining whether the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

31. The circuit of claim 29, wherein the instruction pointer logic circuit comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry.

32. The circuit of claim 31, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit;

a second comparator circuit determining whether the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit.

33. The circuit of claim 29, wherein the reorder buffer entries further comprise a third reorder buffer entry that occurs after the second reorder buffer entry in the sequential program order.

34. The circuit of claim 33, wherein the instruction pointer logic circuit further comprises:

a third adder circuit for determining a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, and an instruction pointer delta value from the third reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the third reorder buffer entry.

35. The circuit of claim 34, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a second comparator circuit determining whether the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a third first comparator circuit determining whether if the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

36. The circuit of claim 33, wherein the instruction pointer logic circuit comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

a circuit for determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry.

37. The circuit of claim 36, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit;

a second comparator circuit determining whether the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit;

a second comparator circuit determining whether the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit.

38. The circuit of claim 33, wherein the reorder buffer entries further comprise a fourth reorder buffer entry that occurs after the third reorder buffer entry in the sequential program order.

39. The circuit of claim 38, wherein the instruction pointer logic circuit further comprises:

a first adder circuit generating a speculative instruction pointer for the first reorder buffer entry by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the first reorder buffer entry indicates a length of the instruction corresponding to the first reorder buffer entry;

a second adder circuit a speculative instruction pointer for the second reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry;

a third adder circuit a speculative instruction pointer for the third reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry; and

a fourth adder circuit a speculative instruction pointer for the fourth reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the third reorder buffer entry, and an instruction pointer delta value from the fourth reorder buffer entry, the instruction pointer delta value from the fourth reorder buffer entry indicating a length of the instruction corresponding to the fourth reorder buffer entry.

40. The circuit of claim 39, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a second comparator circuit determining whether the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a third comparator circuit determining whether the speculative instruction pointer for the third reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a fourth comparator circuit determining whether the speculative instruction pointer for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

41. The circuit of claim 38, wherein the pointer logic circuit comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry;

a circuit for determining a speculative instruction pointer for the third reorder buffer entry equal to a result data value from the third reorder buffer entry;

a circuit for determining a speculative instruction pointer for the fourth reorder buffer entry equal to a result data value from the fourth reorder buffer entry.

42. The circuit of claim 41, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit;

a second comparator circuit determining whether the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit;

a third comparator circuit determining whether the result data value for the third reorder buffer entry is greater than or equal to the instruction pointer limit;

a fourth comparator circuit determining whether the result data value for the fourth reorder buffer entry is greater than or equal to the instruction pointer limit.

43. A computer system, comprising:

a memory subsystem storing a plurality of instructions according to a sequential program order, the memory subsystem coupled for communication over a host bus;

a processor fetching the instructions from the memory subsystem over the host bus and speculatively executing the instructions, the processor comprising a reorder buffer circuit storing a set of result data values for the instructions in a set of reorder buffer entries, wherein the reorder buffer entries comprise a first reorder buffer entry and a second reorder buffer entry such that the instruction corresponding to the second reorder buffer entry occurs after the instruction corresponding to the first reorder buffer entry in the sequential program order, the processor further comprising an instruction pointer logic circuit that determines a speculative instruction pointer for each reorder buffer entry and compares each speculative instruction pointer to an instruction pointer limit, the processor further comprising an event circuit that commits the result data value of each reorder buffer entry to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.

44. The computer system of claim 43, wherein the instruction pointer logic circuit comprises:

a first adder circuit generating a speculative instruction pointer for the first reorder buffer entry by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the first reorder buffer entry indicates a length of the instruction corresponding to the first reorder buffer entry;

a second adder circuit generating a speculative instruction pointer for the second reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry.

45. The computer system of claim 44, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one; and

a second comparator circuit determining whether the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

46. The computer system of claim 43, wherein the instruction pointer logic circuit comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry; and

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry.

47. The computer system of claim 46, wherein the instruction pointer logic circuit further comprises:

a first comparator circuit determining whether the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit;

a second comparator circuit determining whether the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit.

48. A computer system, comprising:

a memory subsystem storing a plurality of instructions according to a sequential program order, the memory subsystem coupled for communication over a host bus;

a processor fetching the instructions from the memory subsystem over the host bus and speculatively executing the instructions, the processor comprising;

a circuit for reading the reorder buffer entries, wherein the reorder buffer entries comprise a first reorder buffer entry and a second reorder buffer entry such that the instruction corresponding to the second reorder buffer entry occurs after the instruction corresponding to the first reorder buffer entry in the sequential program order;

a circuit for determining the speculative instruction pointer for each reorder buffer entry, the speculative instruction pointer indicating an updated instruction pointer for the processor if the corresponding result data value is committed to an architectural state;

a circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit; and

a circuit for committing the result data value of each reorder buffer entry to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.

49. The computer system of claim 48, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry by adding an instruction pointer to an instruction pointer delta value from the first reorder buffer entry, the instruction pointer delta value from the first reorder buffer entry indicates a length of the instruction corresponding to the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry by adding the instruction pointer, the instruction pointer delta value from the first reorder buffer entry, and an instruction pointer delta value from the second reorder buffer entry, the instruction pointer delta value from the second reorder buffer entry indicating a length of the instruction corresponding to the second reorder buffer entry.

50. The computer system of claim 49, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the first reorder buffer entry is greater than or equal to the instruction pointer limit plus one;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the speculative instruction pointer for the second reorder buffer entry is greater than or equal to the instruction pointer limit plus one.

51. The computer system of claim 48, wherein the circuit for determining a speculative instruction pointer each reorder buffer entry comprises:

a circuit for determining a speculative instruction pointer for the first reorder buffer entry equal to a result data value from the first reorder buffer entry;

a circuit for determining a speculative instruction pointer for the second reorder buffer entry equal to a result data value from the second reorder buffer entry.

52. The computer system of claim 51, wherein the circuit for determining whether each speculative instruction pointer exceeds the instruction pointer limit comprises:

a circuit for determining that the speculative instruction pointer for the first reorder buffer entry exceeds the instruction pointer limit if the result data value for the first reorder buffer entry is greater than or equal to the instruction pointer limit;

a circuit for determining that the speculative instruction pointer for the second reorder buffer entry exceeds the instruction pointer limit if the result data value for the second reorder buffer entry is greater than or equal to the instruction pointer limit.

53. A method for executing multiple out of order branch instructions in a same clock cycle, comprising the steps of:

determining a speculative instruction pointer for each executed instruction by adding an instruction pointer to an instruction pointer delta value associated with each instruction executed that comprises a delta value for a particular a instruction plus delta values for instructions preceding the particular instruction;

comparing each speculative instruction pointer to an instruction pointer limit;

determining that a speculative instruction pointer exceeds the instruction pointer limit if the speculative instruction pointer is greater than or equal to the instruction pointer limit plus one;

if the speculative instruction pointer does not exceed the instruction pointer limit, committing a result data entry associated with the speculative instruction pointer to an architectural state;

if the speculative instruction pointer does exceed the instruction pointer limit, generating and storing fault information;

comparing each of the target addresses to the instruction pointer limit;

determining that a target address exceeds the instruction pointer limit if the target address is greater than or equal to the instruction pointer limit; and

for a branch instruction whose speculative instruction pointer does not exceed the instruction pointer limit, calculating an updated instruction pointer value by summing an associated target address with an associated instruction pointer delta value and instruction pointer delta values of other instructions of the instructions executed whose speculative instruction pointers do not exceed the instruction pointer limit.