Flexible processor-driven SCSI controller with buffer memory and local processor memory coupled via separate buses

• US 5,740,466 A
• Filed: 01/25/1996
• Issued: 04/14/1998
• Est. Priority Date: 06/26/1992
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Geldman, John S., Chen, Joe Y., Yoon, Tony J.
• Primary Examiner(s): DINH, DUNG C
• Application Number:
  US08/590,387
• Time in Patent Office: 810 Days
• Field of Search: 395/825, 395/892, 395/894, 395/842, 395/285, 395/309, 395/308, 395/882
• US Class Current: 710/5
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-port buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Claims

1. A controller coupled to a local processor and a local processor memory via a first bus for providing an interface between a disk drive controller and a SCSI bus, the disk drive controller having a disk interface, said controller comprising:

a SCSI-protocol processor having an instruction set which provides programmable control for the operation of said SCSI bus, wherein instructions are provided to said SCSI-protocol processor from an external buffer memory, said buffer memory coupled to said SCSI-protocol processor via a second bus for (i) providing temporary storage for data to be written to said disk drive, (ii) for data read from said disk drive, and (iii) for storing program data and instructions for use by said SCSI-protocol processor, wherein said SCSI-protocol processor executes one instruction in said instruction set and requests a next instruction from the external buffer memory independently from said local processor and said local processor memory;

a buffer manager circuit coupled to said external buffer memory, to said SCSI-protocol processor, and to said disk interface, for controlling the flow of data to and from said buffer memory and allocating space within said buffer memory for the storage of program data and instructions for use by said SCSI-protocol processor and disk interface, wherein control of said external buffer memory by said buffer manager circuit is independent of the local processor and the local processor memory.

2. The controller of claim 1, wherein said instructions are provided to said SCSI-protocol processor by a selected one of the local processor and the external buffer memory.

3. The controller of claim 1, wherein said buffer manager circuit provides burst data to said SCSI-protocol processor.

4. The controller of claim 1, wherein said SCSI-protocol processor executes a predetermined set of instructions adapted to access said buffer memory utilizing a SCSI Address Pointer.

5. The controller of claim 1, wherein said SCSI-protocol processor has a plurality of instruction execution modes.

6. The controller of claim 5, wherein said plurality of instruction execution modes are immediate execution mode, single step execution mode and program execution mode.

7. The controller of claim 1, further comprising an arbitration circuit for requesting exclusive control of a bus coupled to a host computer and repeating the request for exclusive control of the bus until it is made available to the controller.

8. The controller of claim 7, further comprising select/reselect logic circuit for performing predetermined actions necessary to respond to bus-initiated selection and reselection, wherein for bus-initiated selection, the controller is operable in a selected mode.

9. The controller of claim 8, further comprising:

an asynchronous logic circuit for performing asynchronous direct memory access data transfers; and

a synchronous logic circuit for performing synchronous direct memory access data transfers.