High power MOSFET with low on-resistance and high breakdown voltage

• US 5,742,087 A
• Filed: 10/26/1995
• Issued: 04/21/1998
• Est. Priority Date: 10/13/1978
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/548,782
• Time in Patent Office: 908 Days
• Field of Search: 257/342, 257/341, 257/343, 257/339, 257/337, 257/500, 257/502, 257/544
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity epitaxially formed region which is deposited on a high conductivity substrate. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Claims

1. A semiconductor device comprising, in combination:

a thin, flat semiconductor wafer, junction isolation means for dividing said semiconductor wafer into at least first and second laterally separated segments;

said first segment containing at least one power MOSFET device;

said junction isolation means including a P+ sinker diffusion which encloses said first segment;

said at least one power MOSFET device in said first segment including at least first and second spaced base regions each having a respective source region which forms a surface channel region within its respective base region extending from said source region to a respective edge of said respective base region, the respective edges each adjoining a common conduction region; and

a gate means disposed parallel to said channel regions and operable to invert said channel regions;

source electrode means connected to each of said source and base regions and disposed on the top surface of said wafer; and

a drain electrode electrically coupled to said common conduction region, and disposed on the top surface of said wafer.

2. The device of claim 1, wherein said drain electrode is on said top surface of said wafer and is electrically insulated from said source electrode means.

3. The device of claim 1, wherein said first and second spaced base regions are diffusion regions which extend from the top surface of said wafer;

at least one of said base-regions having a closed polygonal topology.

4. The device of claim 3, wherein said first base region has a first relatively deep portion and a second relatively shallow portion, said relatively shallow portion disposed between said first relatively deep portion and said edge of said first base region.

5. A semiconductor device comprising:

a wafer of semiconductor material having first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped, one conductivity type major body portion;

the area of said wafer being divided into at least first and second spaced electrically isolated segments, said first segment including a power device and said second segment including at least one other device;

the power device of said first segment comprising;

at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said first segment and extending from said first surface to a depth beneath said first surface;

the space between said at least first and second base regions defining a common conduction region of said one conductivity type at a given first surface location;

first and second source regions of said one conductivity type formed in said at least first and second base regions, respectively, at first and second first surface locations and extending from said first and second first surface locations to a depth less than said depth of said base regions;

said first and second source regions being laterally spaced along said first surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first surface between said first source region and said common conduction region and between said second source region and said common conduction region, respectively;

source electrode means located on said first surface, connected to said source regions and comprising a first terminal;

gate insulation layer means on said first surface and disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means, overlying said first and second channel regions and comprising a second terminal;

a drain conductive region remote from said common conduction region and extending from said first surface into said major body portion; and

a drain electrode located on said first surface, coupled to said drain conductive region and comprising a third terminal whereby a current path is defined between said source electrode means and said drain electrode which has a first vertical component from said source electrode means through said common conductive region, a lateral component beneath said at least first and second spaced base regions and a second vertical component from beneath said at least first and second spaced base regions to said drain electrode.

6. The device of claim 5 wherein said wafer of semiconductor material further includes a laterally extending relatively thin buried drain region disposed within said drain conductive region and being of said one conductivity type and having a concentration greater than the concentration of said relatively lightly doped major body portion, and extending beneath and spaced from said common conduction region and said at least first and second base regions;

said buried drain region at serving to reduce resistance to lateral current flow between said common conduction region and said drain conductive region.

7. The device of claim 5, wherein each of said at least first and second spaced base regions of said opposite conductivity type has a respective profile which includes a relatively shallow depth region extending from said common conduction region and underlying a corresponding one of said first and second source regions and which includes a respective relatively deep, relatively large radius region extending from said relatively shallow depth region and which is laterally spaced from beneath said corresponding source region on the side of said source region that is away from said common conduction region;

said relatively large radius region at least partially underlying its said corresponding source region.

8. The device of claim 5, wherein said common conduction region is relatively highly doped, compared to said relatively lightly doped major body portion and extends from said given first surface location to a depth greater than the depth of said source regions, whereby resistance to current flow at the junctures between said first and second channel regions and said common conduction region and between said common conduction region and said relatively lightly doped major body portion is reduced.

9. A semiconductor device comprising:

a wafer of semiconductor material having first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped major body portion and being doped with impurities of one conductivity type;

the area of said wafer being divided into at least first and second spaced electrically isolated segments, said first segment including a power device and said second segment including at least one other device;

the power device of said first wafer segment comprising;

at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;

the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location;

first and second source regions of said one conductivity type formed in each of said at least first and second base regions respectively at first and second first surface locations to a depth less than said first depth;

the outer rim of each of said first and second source regions being laterally spaced along said first semiconductor surface from the lateral outer periphery of its base region to define first and second channel regions along said first semiconductor surface between each of said first and second source regions, respectively, and said common conduction region;

source electrode means connected to said source regions;

gate insulation layer means on said first surface, disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means and overlying said first and second channel regions;

a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion;

a drain electrode coupled to said drain conductive region; and

at least said first base region being a cellular polygonal region;

said cellular polygonal region being surrounded by said common conduction region;

said first source region having the shape of an annular ring disposed within said cellular polygonal first base region.

10. The device of claim 9, wherein said common conduction region is relatively highly doped compared to said relatively lightly doped major body portion and extends from said given first semiconductor surface location to a depth greater than the depth of said source region, but less than said first depth of said first and second spaced base regions, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common conduction region and between said common conduction region and said relatively lightly doped major body portion is reduced.

11. The device of claim 9, wherein each of said at least first and second spaced base regions of said opposite conductivity type has a respective profile which includes a relatively shallow depth region extending from said common conduction region and underlying a corresponding one of said first and second source regions and which includes a respective relatively deep, relatively large radius region extending from said relatively shallow depth region and which is laterally spaced from beneath said corresponding source region on the side of said source region that is away from said common conduction region.

12. The device of claim 11, wherein said shallow base regions partially underline their respective source regions.

13. The device of claim 11, wherein said common conduction region is relatively highly doped compared to said relatively lightly doped major body portion and extends from said given first semiconductor surface location to a depth greater than the depth of said source region but less than said first depth of said first and second base regions, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common conduction region and between said common conduction region and said relatively lightly doped major body portion is reduced.