Sealed semiconductor chip

• US 5,742,094 A
• Filed: 08/19/1994
• Issued: 04/21/1998
• Est. Priority Date: 01/25/1993
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ting, Chiu H.
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/293,120
• Time in Patent Office: 1,341 Days
• Field of Search: 257/640, 257/641, 257/786, 257/760, 257/737, 257/738, 257/620, 257/787, 437/227, 437/228, 438/114, 438/113
• US Class Current: 257/620
• CPC Class Codes: G11C 16/18 Circuits for erasing optically
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Claims

1. A semiconductor chip comprising

a semiconductor substrate, said semiconductor substrate having a first surface;

a plurality of integrated circuit devices extending from said first surface, said integrated circuit devices being separated by a scribe lane, said scribe lane having a bottom surface and at least one side surface extending from said bottom surface to a top dielectric layer located on at least one of said integrated circuit devices, said first surface of said substrate defining said bottom surface of said scribe lane, each of said integrated circuit devices comprising at least one conductive layer and one dielectric layer, said dielectric layer including at least one bonding pad opening having a side wall extending from said conductive layer to a top surface of said integrated circuit device, said conductive layer defining a bottom surface of said bonding pad opening, said bottom surface of said bonding pad opening comprising a first portion and a second portion; and

a first protective film covering said top surface of said integrated circuit device, said side and bottom surfaces of said scribe lane, said side wall and said first portion of said bottom surface of said bonding pad opening; and

a second protective film covering said second portion of said bottom surface of said bonding pad opening and a portion of said first protective film.

2. The semiconductor chip in claim 1 wherein said first protective film comprises a moisture resistant material, and wherein said first protective film is transparent to ultraviolet light.

3. The semiconductor chip in claim 2 wherein said moisture resistant material comprises silicon nitride.

4. The semiconductor chip in claim 3 wherein said thickness of said first protective film is no greater than 1000 angstroms.

5. The semiconductor chip in claim 1 wherein said second protective film is an electrically conductive passivation layer, said electrically conductive passivation layer comprising a non-corrosive material.

6. The semiconductor chip in claim 5 wherein said non-corrosive material comprises electroless nickel or nickel alloy.

7. A semiconductor chip comprising

a semiconductor substrate, said semiconductor substrate having a first surface;

a plurality of integrated circuit devices extending from said first surface, said integrated circuit devices being separated by a scribe lane, said scribe lane having a bottom surface and at least one side surface extending from said bottom surface to a top dielectric layer located on at least one of said integrated circuit devices, said first surface of said substrate defining said bottom surface of said scribe lane, each of said integrated circuit devices comprising at least one conductive layer and one dielectric layer, said dielectric layer including at least one bonding pad opening having a side wall extending from said conductive layer to a top surface of said integrated circuit device, said conductive layer defining a bottom surface of said bonding pad opening, each of said bottom and said side surfaces of said bonding pad opening comprising a first portion and a second portion; and

a first protective film covering said first portion, said first protective film comprising a moisture resistant material, said first protective film being transparent to ultraviolet light; and

a second protective film covering said second portion.

8. The semiconductor chip in claim 7 wherein said moisture resistant material comprises silicon nitride.

9. The semiconductor chip in claim 8 wherein said thickness of said first protective film is no greater than 1000 angstroms.

10. The semiconductor chip in claim 7 wherein said second protective film is an electrically conductive passivation layer, said electrically conductive passivation layer comprising a non-corrosive material.

11. The semiconductor chip in claim 10 wherein said non-corrosive material comprises electroless nickel or nickel alloy.

12. A semiconductor chip comprising:

a semiconductor substrate, said semiconductor substrate having a first surface;

a plurality of integrated circuit devices extending from said first surface, said integrated circuit devices being separated by a scribe lane, said scribe lane having a bottom surface and at least one side surface extending from said bottom surface to a top dielectric layer located on at least one of said integrated circuit devices, said first surface of said substrate defining said bottom surface of said scribe lane, each of said integrated circuit devices comprising at least one conductive layer and a plurality of dielectric layers, said plurality of dielectric layers including at least one bonding pad opening having a side wall extending from said conductive layer to a top surface of said integrated circuit device, said conductive layer defining a bottom surface of said bonding pad opening, said bottom surface of said bonding pad opening comprising a first portion and a second portion;

a first protective film disposed between said plurality of dielectric layers and covering said top surface of said integrated circuit device, said side and bottom surfaces of said scribe lane, said side wall and said first portion of said bottom surface of said bonding pad opening; and

a second protective film covering said second portion of said bottom surface of said bonding pad opening and a portion of said first protective film.