Method of fabricating planar regions in an integrated circuit

• US 5,742,095 A
• Filed: 11/20/1996
• Issued: 04/21/1998
• Est. Priority Date: 12/22/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Bryant, Frank Randolph, Hodges, Robert Louis
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/752,749
• Time in Patent Office: 517 Days
• Field of Search: 257/510, 257/519, 257/640, 257/750, 257/752, 257/755, 257/305, 257/395, 257/396, 257/647
• US Class Current: 257/647
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76216 introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.

Claims

1. A structure consisting of a portion of a semiconductor integrated circuit formed at a surface of a body, comprising:

a plurality of active regions at the surface;

an isolation structure formed above the surface and into a recess of the surface between a pair of the plurality of active regions;

an undoped oxide layer disposed over at least a portion of the surface of each active regions within the pair of active regions;

a doped first polysilicon layer disposed over the oxide layer wherein the first polysilicon layer over the oxide layer in one active region forms a gate electrode and the first polysilicon layer over the oxide layer forms an interconnect in the other active region within the pair of active regions; and

wherein an upper surface of the first polysilicon layer is substantially planar with a central portion of the upper surface of the isolation structure; and

a nitride spot at an interface between the isolation structure and the surface of the body.

2. A structure consisting of a portion of a semiconductor integrated circuit formed at a surface of a body, comprising:

a plurality of active regions at the surface;

an isolation structure formed above the surface and into a recess of the surface between a pair of the plurality of active regions;

an undoped oxide layer disposed over at least a portion of the surface of each active regions within the pair of active regions; and

a doped first polysilicon layer disposed over the oxide layer wherein the first polysilicon layer over the oxide layer in one active region forms a gate electrode and the first polysilicon layer over the oxide layer forms an interconnect in the other active region within the pair of active regions; and

wherein an upper surface of the first polysilicon layer is substantially planar with a central portion of the upper surface of the isolation structure, wherein the oxide layer is a composite layer comprising a thin nitride layer over the oxide layer.

3. The structure of claim 2, wherein the composite layer further comprises a seal oxide layer disposed over the thin nitride layer.

4. A structure consisting of a portion of a semiconductor integrated circuit formed at a surface of a body, comprising:

a gate oxide layer overlying a portion of an active region;

a polysilicon layer overlying the gate oxide layer wherein the gate oxide layer and the polysilicon layer comprise a gate electrode;

a field oxide region adjacent the active region wherein an upper surface of a central portion of the field oxide region is substantially planar with an upper surface of the gate electrode; and

a nitride spot at an interface between the field oxide region and the active region.

5. A structure consisting of a portion of a semiconductor integrated circuit formed at a surface of a body, comprising:

a gate oxide layer overlying a portion of an active region;

a polysilicon layer overlying the gate oxide layer wherein the gate oxide layer and the polysilicon layer comprise a gate electrode; and

a field oxide region adjacent the active region wherein an upper surface of a central portion of the field oxide region is substantially planar with an upper surface of the gate electrode, wherein the gate oxide layer is a composite layer comprising a thin nitride layer over the oxide layer.

6. The structure of claim 5, wherein the nitride layer has a thickness of between approximately 10 to 200 angstroms.

7. The structure of claim 5, wherein the gate oxide layer is a composite layer comprising a seal oxide layer over the thin nitride layer.

8. The structure of claim 7, wherein the seal oxide layer has thickness of between approximately 10 to 30 angstroms.