Dynamically programmable gate array with multiple contexts

• US 5,742,180 A
• Filed: 02/10/1995
• Issued: 04/21/1998
• Est. Priority Date: 02/10/1995
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Brown, Jeremy, Eslick, Ian, Tau, Edward, Chen, Derrick, Bolotski, Michael, DeHon, Andre, Knight, Thomas F. Jr.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/386,851
• Time in Patent Office: 1,166 Days
• Field of Search: 326/38-40, 326/46
• US Class Current: 326/40
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal. Since the contexts information is stored on the gate array, and specifically locally, the context signal can change as fast as every clock cycle of the programmable gate array. To increase functionality, context memory arrays, which store context programming information, are separately addressable so that a new truth table is storable in a first one of the context memory arrays while a truth table of a second one of the context memory arrays is dictating the logic operations performed by the gates. As a result, the functionality of each programmable gate can be increased by increasing the number of available functions for that programmable gate.

Claims

1. An integrated dynamically programmable logic array, comprising:

at least a two dimensional array of programmable logic elements, each one of the logic elements receiving plural input logic signals from plural other logic elements and including locally stored multiple contexts dictating different combinatorial logic operations performed by the logic elements; and

a context signal source that provides a context signal, indicating an active one of the contexts, commonly to the programmable logic elements of the array; and

wherein the contexts for each one of the logic elements are individually accessible so that a new context can be loaded into the logic elements while another context is controlling logic operations of the logic elements.

2. A programmable logic array as described in claim 1, wherein the context signal source provides the context signal up to every cycle of the programmable logic array.

3. A programmable logic array as described in claim 1, wherein the context signal source generates plural context signals that dictate contexts for regions of the array of the logic elements.

4. A programmable logic array as described in claim 1, wherein each one of the logic elements receives at least four input logic signals from other logic elements of the array and generates at least one output logic signal in response to the input logic signals.

5. A programmable logic array as described in claim 1, further comprising a logic element interconnect for transmitting logic signals between logic elements.

6. A programmable logic array as described in claim 5, wherein the interconnect includes stored multiple contexts for dictating routing of the logic signals between the logic elements.

7. A programmable logic array as described in claim 6, wherein the contexts for the interconnect are individually accessible so that a new context can be stored into the interconnect while another context is controlling a routing operation performed by the interconnect.

8. A programmable logic array as described in claim 6, wherein the interconnect comprises a crossbar-type interconnect.

9. A programmable logic array as described in claim 1, wherein the logic elements are adaptable to enable transmission of logic signals directly between logic elements without intervening latching.

10. A programmable logic array as described in claim 1, wherein the logic elements are programmable gates.

11. A programmable logic array as described in claim 1, further comprising a multilevel logic element interconnect that transmits logic signals between logic elements.

12. A programmable logic array as described in claim 11, wherein the interconnect includes stored multiple contexts that dictate routing of the logic signals between the logic elements.

13. A programmable logic array as described in claim 12, wherein the context information is stored in memories distributed throughout the interconnect.

14. A programmable logic array as described in claim 11, wherein the interconnect comprises a level-one interconnect that transmits logic signals between near-neighborhood logic elements.

15. A programmable logic array as described in claim 14, wherein the interconnect further comprises a level-two interconnect that transmits logic signals between subarrays of the logic elements.

16. A programmable logic array as described in claim 14, wherein the level one interconnect further transmits logic signals globally across the array.

17. A programmable logic array as described in claim 6, wherein the contexts of the interconnect are stored in context memory vectors holding encoded states for switching elements of the interconnect.

18. An integrated dynamically programmable logic array, comprising:

at least a two dimensional array of programmable logic elements, each one of the logic elements receiving plural input logic signals from plural other logic elements and including locally stored multiple contexts dictating different combinatorial logic operations performed by the logic elements; and

a context signal source that provides a context signal, indicating an active one of the contexts, commonly to the programmable logic elements of the array; and

wherein the contexts for the logic elements are stored in separately addressable context memory vectors holding truth tables for the combinatorial logic operations so that a new truth table is storable in a first one of the context memory vectors while a truth table of a second one of the context memory vectors is dictating the logic operations performed by the logic elements.

19. An integrated dynamically programmable gate array, comprising:

a two dimensional array of programmable gates, each one of the gates including;

at least two separately addressable and programmable memories for storing truth tables of different contexts corresponding to different combinatorial logic operations;

a memory selector for activating one of truth tables in response to a context signal;

a multiplexer generating an output logic signal by addressing the activated memory in response to input logic signals from other gates in the two dimensional array; and

a gate interconnect for transmitting the output logic signals received from the gates of the array as the input logic signals to the gates of the array; and

a context selector for generating the context signal commonly received by the gates of the array.

20. A method for operating an integrated dynamically programmable gate array including a two dimensional array of programmable gates, the method comprising:

providing each one of the gates with plural input logic signals from plural other gates;

locally storing multiple contexts at the gates;

performing different combinatorial logic operations with the gates by accessing the multiple contexts;

providing a context signal indicating an active one of the contexts, the active context dictating the logic operation of the gates;

commonly providing the context signal to the programmable gates of the arrays

individually accessing the contexts; and

loading new contexts into the programmable gates while other contexts are controlling logic operations of the gates.

21. A method as described in claim 20, further comprising generating a new context signal in response to a clock signal.

22. A method as described in claim 20, further comprising providing a multilevel logic element interconnect that transmits logic signals between the programmable gates.

23. A method as described in claim 22, further comprising storing multiple contexts that dictate routing of the logic signals between the programmable gates.

24. A method as described in claim 22, further comprising storing the context information in memories distributed throughout the interconnect.

25. A method as described in claim 22, further comprising providing a level-one interconnect that transmits logic signals between near-neighborhood programmable gates.

26. A method as described in claim 25, further comprising providing a level-two interconnect that transmits logic signals between subarrays of the programmable gates.

27. A method as described in claim 25, further comprising the level-one interconnect transmitting logic signals globally across the array.

28. A method as described in claim 20, further comprising:

controlling the routing of logic signals between the programmable gates over an interconnect in response to the context signal; and

storing contexts of the interconnect in context memory vectors holding encoded states for switching elements of the interconnect.