Field effect transistor cable television line amplifier

• US 5,742,205 A
• Filed: 07/25/1996
• Issued: 04/21/1998
• Est. Priority Date: 07/27/1995
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Veneman, Steven, Siclari, Scott R., Cowen, Martin A., Thompson, Leo J.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/686,022
• Time in Patent Office: 635 Days
• Field of Search: 330/269, 330/271, 330/275, 330/276, 330/311
• US Class Current: 330/269
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/63 the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/1935 with junction-FET devices
• CPC Class Codes: H03F 3/265 with field-effect transistors only
• CPC Class Codes: H03G 1/007 using FET type devices

Abstract

An amplifier circuit for a cable access television line amplifier has a circuit input and a circuit output and includes a first cascode amplifier having a first input and a first output, and a second cascode amplifier having a second input and a second output where the second cascode amplifier is coupled in a push-pull arrangement with the first cascode amplifier. The amplifier circuit further includes input circuitry for coupling the circuit input to the first and second inputs and output circuitry for coupling the first and second outputs to the circuit output. The first cascode amplifier includes a first field effect transistor coupled to the first input; the second cascode amplifier includes a second field effect transistor coupled to the second input; the first cascode amplifier further includes a third field effect transistor coupled to the first output; and the second cascode amplifier further includes a fourth field effect transistor coupled to the second output. An alternative amplifier circuit for a cable access television line amplifier has a circuit input and a circuit output and includes a first transimpedance amplifier having a first input and a first output, and a second transimpedance amplifier having a second input and a second output where the second transimpedance amplifier being coupled in a push-pull arrangement with the first transimpedance amplifier.

Claims

1. In a cable access television line amplifier, an amplifier circuit having a circuit input and a circuit output, the amplifier circuit comprising:

a first amplifier having a first input and a first output;

a second amplifier having a second input and a second output, the second amplifier being coupled in a push-pull arrangement with the first amplifier;

input circuitry for coupling the circuit input to the first and second inputs; and

output circuitry for coupling the first and second outputs to the circuit output,

wherein the first amplifier includes a first field effect transistor coupled to the first input,

wherein the second amplifier includes a second field effect transistor coupled to the second input,

wherein the first amplifier further includes a third field effect transistor coupled to the first output,

wherein the second amplifier further includes a fourth field effect transistor coupled to the second output;

wherein a fifth field effect transistor is coupled between the first transistor and the first output; and

wherein a sixth field effect transistor is coupled between the second transistor and the second output.

2. The amplifier circuit of claim 1, wherein each of the first, second, third and fourth transistors is a gallium arsenide field effect transistor.

3. The amplifier circuit of claim 1, wherein:

the first amplifier is a first cascode amplifier; and

the second amplifier is a second cascode amplifier.

4. The amplifier circuit of claim 3, wherein each of the first, second, third and fourth transistors are gallium arsenide field effect transistors.

5. The amplifier circuit of claim 3, wherein each of the first, second, third and fourth transistors are dual gate gallium arsenide field effect transistors.

6. The amplifier circuit of claim 1, wherein at least one of the input circuitry and the output circuitry includes a balun.

7. The amplifier circuit of claim 1, wherein the input circuitry includes a balun, the balun being capable of splitting an input signal at the circuit input into a first signal at the first input and a second signal at the second input, a first amplitude of the first signal being substantially equal to a second amplitude of the second signal, a phase difference between the first signal and the second signal being 180 degrees plus or minus a phase offset, the phase offset being no more than 2 degrees over a predetermined range of frequencies.

8. The amplifier circuit of claim 7, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

9. The amplifier circuit of claim 1, wherein the output circuitry includes a balun, the balun being capable of combining a first signal from the first output with a second signal from the second output to form an output signal at the circuit output, a first amplitude of the first signal being substantially equal to a second amplitude of the second signal, a phase difference between the first signal and the second signal being 180 degrees plus or minus a phase offset, the phase offset being no more than 2 degrees over a predetermined range of frequencies.

10. The amplifier circuit of claim 9, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

11. The amplifier circuit of claim 1, wherein the input circuitry includes a balun, the balun being capable of splitting an input signal at the circuit input into a first signal at the first input and a second signal at the second input, the first and second signals being substantially out of phase, a first amplitude of the first signal being equal to a second amplitude of the second signal plus or minus an amplitude imbalance, the amplitude imbalance being no more than 0.5 dB over a predetermined range of frequencies.

12. The amplifier circuit of claim 11, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

13. The amplifier circuit of claim 1, wherein the output circuitry includes a balun, the balun being capable of combining a first signal from the first output with a second signal from the second output to form an output signal at the circuit output, the first and second signals being substantially out of phase, a first amplitude of the first signal being equal to a second amplitude of the second signal plus or minus an amplitude imbalance, the amplitude imbalance being no more than 0.5 dB over a predetermined range of frequencies.

14. The amplifier circuit of claim 13, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

15. The amplifier circuit of claim 1, wherein the input circuitry includes a balun, the balun being capable of splitting an input signal at the circuit input into a first signal at the first input and a second signal at the second input, a phase difference between the first signal and the second signal being 180 degrees plus or minus a phase offset, the phase offset being no more than 2 degrees over a predetermined range of frequencies, a first amplitude of the first signal being equal to a second amplitude of the second signal plus or minus an amplitude imbalance, the amplitude imbalance being no more than 0.5 dB over the predetermined range of frequencies.

16. The amplifier circuit of claim 15, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

17. The amplifier circuit of claim 1, wherein the output circuitry includes a balun, the balun being capable of combining a first signal from the first output with a second signal from the second output to form an output signal at the circuit output, a phase difference between the first signal and the second signal being 180 degrees plus or minus a phase offset, the phase offset being no more than 2 degrees over a predetermined range of frequencies, a first amplitude of the first signal being equal to a second amplitude of the second signal plus or minus an amplitude imbalance, the amplitude imbalance being no more than 0.5 dB over the predetermined range of frequencies.

18. The amplifier circuit of claim 17, wherein the predetermined range of frequencies includes frequencies from 40 MHz to 750 MHz.

19. The amplifier circuit of claim 1, wherein at least one of the input circuitry and the output circuitry includes a balun and at least one capacitor.

20. The amplifier circuit of claim 1, wherein the input circuitry includes a balun and at least one capacitor selected so that an input impedance at the circuit input matches a paralleled impedance at the first and second inputs over a predetermined range of frequencies.

21. The amplifier circuit of claim 1, wherein the output circuitry includes a balun and at least one capacitor selected so that an output impedance at the circuit output matches a paralleled impedance at the first and second outputs over a predetermined range of frequencies.

22. The amplifier circuit of claim 1, wherein the input circuitry includes a balun, the balun including a magnetic core, the magnetic core being saturable so that the circuit input is insensitive to static discharge.

23. The amplifier circuit of claim 1, wherein the output circuitry includes a balun, the balun including a magnetic core, the magnetic core being saturable so that the circuit output is insensitive to static discharge.

24. The amplifier circuit of claim 1, wherein the first amplifier includes a parallel arrangement of a resistor and an inductor coupled between the third field effect transistor and the first output.

25. The amplifier circuit of claim 1, wherein:

the first field effect transistor includes a gate and a drain; and

the first amplifier further includes a capacitor and an inductor and first and second resistors, the first resistor being coupled between the gate and the first input, a series arrangement of the second resistor and the capacitor and the inductor being coupled between the drain and the first input.

26. The amplifier circuit of claim 1, further comprising a low pass filter coupled between the first and third field effect transistors.

27. The amplifier circuit of claim 1, further comprising a filter coupled between the first and third field effect transistors, the filter including a capacitor and a series arrangement of a resistor and an inductor, the capacitor being coupled between a ground and a connection point between the resistor and the inductor.

28. The amplifier circuit of claim 1, wherein:

the first and second amplifiers are amplifiers formed in a first monolithic integrated amplifier;

the amplifier circuit further includes a second monolithic integrated amplifier coupled between the first monolithic integrated amplifier and the output circuitry, the second monolithic integrated circuit including a third amplifier and a fourth amplifier, the fourth amplifier being coupled in a push-pull arrangement with the third amplifier;

the third amplifier includes a fifth field effect transistor coupled to the first output;

the fourth amplifier includes a sixth field effect transistor coupled to the second output;

the third amplifier further includes a seventh field effect transistor coupled to the output circuitry; and

the fourth amplifier further includes an eighth field effect transistor coupled to the output circuitry.

29. The amplifier circuit of claim 28, wherein:

each of the first and second monolithic integrated amplifiers are selected from a family of monolithic integrated amplifiers, each member of the family of monolithic integrated amplifiers having been designed to optimally operate at a unique optimal bias; and

an optimal bias of the first monolithic integrated amplifier being different than an optimal bias of the second monolithic integrated amplifier.

30. The amplifier circuit of claim 1, wherein the first and second amplifiers are amplifiers formed in a monolithic integrated amplifier, the monolithic integrated amplifier being removably attachable to the amplifier circuit by means of a connection, the connection including one of plug-in sockets and solder connections.

31. The amplifier circuit of claim 1 operable over a predetermined range of frequencies, the predetermined range of frequencies including one of frequencies from 40 MHz to 750 MHz and frequencies from 1 MHz to 40 MHz.

32. In a cable access television line amplifier, an amplifier circuit having a circuit input and a circuit output, the amplifier circuit comprising:

a first amplifier having a first input and a first output;

a second amplifier having a second input and a second output, the second amplifier being coupled in a push-pull arrangement with the first amplifier;

input circuitry for coupling the circuit input to the first and second inputs; and

output circuitry for coupling the first and second outputs to the circuit output,

wherein the first amplifier includes a first field effect transistor coupled to the first input, said first field effect transistor having a gate and a drain, a capacitor, an inductor and first and second resisters, the first resistor coupled between the gate and the first input, a series arrangement of the second resistor and the capacitor and the inductor coupled between the drain and the first input, and further including a fifth field effect transistor coupled between the drain of the first field effect transistor and the first output,

wherein the second amplifier includes a second field effect transistor coupled to the second input,

wherein the first amplifier further includes a third field effect transistor coupled to the first output,

wherein the second amplifier further includes a fourth field effect transistor coupled to the second output.