Digital-to-analog converter circuit using current mirror circuit for conversion of law-order bits

• US 5,742,245 A
• Filed: 05/07/1996
• Issued: 04/21/1998
• Est. Priority Date: 05/08/1995
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Noro, Masao
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): KOST, JASON L
• Application Number:
  US08/644,645
• Time in Patent Office: 714 Days
• Field of Search: 341/131, 341/135, 341/144, 341/145, 341/150
• US Class Current: 341/144
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/745 with weighted currents

Abstract

A digital-to-analog converter circuit is configured by a digital-to-analog converter receiving data of m bits (where `m` is an integer arbitrarily selected), a voltage-follower circuit containing an operational amplifier, a current-mirror circuit and a current-switching circuit. Herein, the data of m bits are extended by bits b_H and b_L in low-order positions thereof, wherein b_H is placed in a higher order than b_L. A noninverting input of the operational amplifier is connected to an output of the digital-to-analog converter; and a feedback resistor is connected between an inverting input and an output of the operational amplifier. The current-mirror circuit, using MOS transistors, provides two constant currents I_H and I_L in response to the bits b_H and b_L respectively, wherein a relationship between the constant currents I_H and I_L is defined by an equation of I_H =2×I_L. The current-switching circuit, which is connected between the current-mirror circuit and the voltage-follower circuit, is designed to selectively switch the two constant currents to be supplied to the inverting input of the operational amplifier in accordance with values of the bits b_H and b_L. Thanks to the configuration of the digital-to-analog converter circuit, the feedback resistor and the current-mirror circuit can be designed for small areas. Hence, it is possible to easily extend a number of bits without greatly enlarging the size of the digital-to-analog circuit.

Claims

1. A digital-to-analog converter circuit, the digital-to-analog converter circuit comprising:

a digital-to-analog converter for receiving data of m bits (where `m` is an integer arbitrarily selected), wherein the data of m bits are extended by bits b_H and b_L in low-order positions thereof and b_H is placed in a higher order than b_L ;

a voltage-follower circuit containing an operational amplifier whose noninverting input is connected to an output of the digital-to-analog converter, wherein a feedback resistor is connected between an inverting input and an output of the operational amplifier;

a current-mirror circuit for providing two constant currents I_H and I_L in response to the bits b_H and b_L respectively, wherein a relationship between the constant currents I_H and I_L is defined by an equation of I_H =2×

I_L ; and

a current-switching circuit, connected between the current-mirror circuit and the voltage-follower circuit, for selectively providing the two constant currents to the inverting input of the operational amplifier in accordance with values of the bits b_H and b_L.

2. A digital-to-analog converter circuit according to claim 1, wherein in the current-mirror circuit, a reference current is subjected to current-mirror operation, using MOS transistors Q_H and Q_L, so that the constant currents I_H and I_l are created, wherein the relationship between the constant currents I_H and I_L is set by adjusting measurements of the MOS transistors Q_H and Q_L.

3. A digital-to-analog converter circuit according to claim 1, wherein the current-switching circuit is configured by two pairs of MOS transistors, each pair of MOS transistors is connected to the current-mirror circuit, and one of the MOS transistors in each pair is selectively tuned on such that each of the constant current I_H and I_L is selectively provided to the inverting input of the operational amplifier in accordance with a value of each of the bits b_H and b_L.

4. A digital-to-analog converter circuit, the digital-to-analog converter circuit comprising:

a digital-to-analog converter for receiving data of m bits which are placed in high orders of input data of (m+n) bits (where `m` and `n` are integers arbitrarily selected);

a voltage-follower circuit containing an operational amplifier whose noninverting input is connected to an output of the digital-to-analog converter, wherein a feedback resistor is connected between an inverting input and an output of the operational amplifier;

a current-mirror circuit for providing a plurality of constant currents, a number of which is set at `n`, in response to n bits which are placed in low orders of the input data of (m+n) bits; and

a current-switching circuit, connected between the current-mirror circuit and the voltage-follower circuit, for selectively providing the plurality of constant currents to the inverting input of the operational amplifier in accordance with values of the n bits.

5. A digital-to-analog converter circuit, the digital-to-analog converter circuit comprising:

a digital-to-analog converter means for receiving data of m bits which are placed in high orders of input data of(m+n) bits (where `m` and `n` are integers arbitrarly selected);

a signal summing means containing an operational amplifier whose noninverting input is connected to an output of the digital-to-analog converter means, wherein a feedback resistor is connected between an inverting input and an output of the operational amplifier;

a current source means for providing a plurality of constant currents, a number of which is set at `n`, in response to n bits which are placed in low orders of the input data of (m+n) bits; and

a current-switching means, connected between the current source means and the signal summing means, for selectively providing the plurality of constant currents to the inverting input of the operational amplifier in accordance with values of the n bits.