AC plasma gas discharge gray scale graphic, including color and video display drive system

• US 5,742,265 A
• Filed: 01/21/1993
• Issued: 04/21/1998
• Est. Priority Date: 12/17/1990
• Status: Expired due to Term

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Photonics Systems Corporation
• Inventors: Stoller, Ray A., Stalker, Michael B.
• Primary Examiner(s): NGUYEN, CHANH DUY
• Application Number:
  US08/008,239
• Time in Patent Office: 1,916 Days
• Field of Search: 340/771, 340/798, 340/799, 340/793, 340/703, 340/701, 340/750, 340/747, 364/518, 364/521, 395/162, 395/163, 395/164, 345/60, 345/61, 345/62, 345/63, 345/64, 345/65, 345/77, 345/41
• US Class Current: 345/60
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/293 for address discharge
• CPC Class Codes: G09G 3/294 for lighting or sustain discharge
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes
• CPC Class Codes: G09G 3/297 using opposed discharge type panels
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A novel drive system is described for AC plasma (ACP) gas discharge flat bistable matrix panels on which real-time video and computer graphics, both with pixel by pixel gray scale are displayed. The drive scheme increases scan speed, reduces complexity and minimizes circuitry required to operate the video and computer graphics gray scale images on the ACP display through: a) unique application of standard high density memory IC architecture, and b) unique panel drive waveform technique. Flicker is avoided with an interlaced framerate of 46 Hz and non-sequential pixel row scanning. The unique panel drive scheme allows high speed operation to avoid flicker in the ACP panel for real time gray scale video and graphic images. Because of the high speed addressing requirements, the panel waveform techniques apply all of the drive voltages to the ACP panel from the row (Y) axis and only selective cancellation voltage from the column (X) axis. This technique results in ground based data transfer from the memory circuits to the column driver ICs, and eliminates significant level shifting through multiple parallel isolation circuits such as transformers or optical couplers. Avoidance of isolation circuits in the X-axis allows higher speed transfer of data into column drivers. The panel addressing requirements for pixel-by-pixel gray scale is minimized through geometric accumulation of pixel on-time per frame. At least 64 levels of gray scale are provided in standard neon ACP displays with pixel rows of 256, 480 and 512, for example.

Claims

1. A drive system for an AC plasma display panel having pixel elements located by column (X) and row (Y) electrodes, X electrode driver means connected to the X electrodes and Y driver means connected to the Y electrodes and a source of N-bit word signals representing the amplitude of video signals for each pixel element located by the crossing of said X and Y electrodes and means for translating said N-bit word to driver signals for controlling the X and Y driver means to cause each pixel element to selectively emit light output storage elements, a first voltage driver means connected between the output storage elements and said X electrodes for supplying X axis control voltages to said column X electrodes, said first voltage driver means being dedicated solely to high speed pixel control which is logic ground based and a second voltage driver means connected between said output storage elements and said row (Y) electrodes for supplying Y axis control voltages to said row electrodes, said X axis control voltages being applied to said column (X) electrodes at selected times to selectively cancel said Y axis control voltage.

5. The invention defined in any one of claims 1-4 wherein said flat panel, matrix display device is a full color AC plasma display which employs pixel-by-pixel gray scale within each color channel.

2. An AC plasma display system having an array of display pixels with memory in a flat panel, matrix display device, a source of digital signals wherein an N-bit word represents the amplitude of pixel data for each pixel element, said matrix display device having column (X) and row (Y) electrodes, column (X) and row (Y) driver means connected to the column (X) and row (Y) electrodes, respectively, and locating each said pixel element with memory, driver means includes (1) a first voltage driver means connected between said output storage elements and said column (X) electrode for supplying column (X) axis control voltages to said column (X) electrodes, said first voltage driver being dedicated solely to high speed pixel control which is logic ground based, and (2) second voltage driver means connected between said output storage elements and said row (Y) electrodes for supplying Y axis control voltages to said row electrodes, said X axis control voltages being applied to said column (X) electrodes at selected times to selectively cancel said Y axis control voltage, and means for translating said N-bit word to driver signals for controlling said driver means and cause each said pixel element with memory to selectively emit light and without bit rotation or translation to said driver means, said driver means for said row (Y) electrodes developing and applying a periodic sustainer voltage to said row (Y) electrodes, said means for translating comprising an array of parallel input first storage elements for capturing video data in columns of pixel data bytes and outputting in serial form from said parallel input storage elements said columns of pixel data bytes, an array of output storage elements for serially shifting pixel data bytes from said array of parallel input storage elements to said array of output storage elements at one time and means for parallel transferring said pixel data bytes from said output storage elements at the same time as said driver signals for controlling said drive means and cause each selected pixel element with memory to selectively emit light in said matrix display device.

3. The display system defined in claim 2 in which there are write, erase and sustain sequences for said pixels and wherein said means supplying X axis and Y axis control voltages to said column (X) and row (Y) electrodes so as to non-selectively erase each pixel row to be addressed while no column (X) control voltage is applied during the write sequence and after all active pixels have been erased, selectively writing pixels by applying simultaneous combinations of X and Y axis control voltages to selected pixels in a row.

4. The display system defined in claim 2 in which there are write, erase and sustain sequences for said pixels and wherein said driver means supply X axis and Y axis control voltages to said column (X) and row (Y) electrodes so as to non-selectively write each pixel row to be addressed while no column (X) control voltage is applied during the erase sequence and then selectively extinguishing pixels in said row by applying simultaneous combinations of X and Y axis control voltages to selected pixels in a row.