Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system

• US 5,742,510 A
• Filed: 02/21/1996
• Issued: 04/21/1998
• Est. Priority Date: 04/19/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Jones, Edwin R., Scepanovic, Ranko, Koford, James S., Boyle, Douglas B., Rostoker, Michael D.
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/604,181
• Time in Patent Office: 790 Days
• Field of Search: 364/468, 364/488-493, 364/468.03, 364/468.01, 364/468.28, 395/10, 395/13, 395/904, 395/912, 395/919, 395/920, 395/921
• US Class Current: 700/97
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

Claims

1. A method of optimizing a cell placement for an integrated circuit chip, comprising the steps of:

(a) routing said cell placement;

(b) identifying congested areas of said routing;

(c) selectively applying a congestion reduction algorithm only within said congested areas to alter said cell placement in said congested areas;

(d) computing a cell placement fitness; and

(e) if said cell placement fitness is below a predetermined value, repeating steps (b) to (d).

2. A method as in claim 1, in which step (e) further comprises repeating step (a).

3. A method as in claim 1, in which:

said placement comprises a plurality of nets of cells; and

step (a) comprises routing said nets in parallel.

4. A method as in claim 1, in which step (a) comprises the substeps of:

(f) dividing said placement into a plurality of predetermined areas; and

(g) routing said predetermined areas in parallel.

5. A method as in claim 1, in which step (c) comprises applying said congestion reduction algorithm to said congested areas in parallel.

6. A method as in claim 5, in which step (c) comprises moving selected cells out of said congested areas.

7. A method as in claim 5, in which step (c) comprises relocating selected cells such that routing thereof does not pass through said congested areas.

8. A method as in claim 7, in which step (c) comprises the substeps of:

(f) relocating said selected cells in a predetermined manner;

(g) rerouting nets of cells that include said selected cells; and

(h) repeating steps (f) and (g) if said rerouting passes through said congested areas.

9. A method as in claim 8, comprising performing steps (f), (g) and (h) on said selected cells and said nets respectively in parallel.

10. A method as in claim 8, in which step (g) comprises applying a Steiner tree algorithm for rerouting said nets.

11. A method as in claim 7, in which step (c) comprises selecting said cells for relocation as having high values of interconnect congestion.

12. A method as in claim 7, in which step (c) comprises selecting said cells for relocation if routing thereof passes through said congested areas.

13. A method as in claim 7, in which step (c) comprises selecting said cells for relocation if said cells are outside perimeters that surround other cells in nets to which said selected cells are connected respectively.

14. A method as in claim 13, in which step (c) comprises relocating said selected cells inside said perimeters respectively.

15. A method as in claim 14, in which step (c) comprises relocating said selected cells to centroids of said perimeters respectively.

16. A method as in claim 1, in which:

step (c) comprises relocating selected cells without rerouting said placement; and

the method further comprises the steps of;

(f) calculating an amount of error in said routing created by step (c); and

(g) repeating step (a) if said amount of error exceeds a predetermined value.

17. A method as in claim 16, in which steps (f) and (g) are performed after step (c).

18. A method as in claim 1, in which step (c) comprises the substeps of:

(f) dividing said placement into a plurality of predetermined areas; and

(g) applying said congestion reduction algorithm to said predetermined areas in parallel.

19. A method as in claim 18, in which step (g) comprises the substeps of:

(h) relocating selected cells without rerouting said placement;

(i) calculating amounts of error in said routing created by step (h) in each of said predetermined areas respectively; and

(j) repeating step (a) if said amount of error in any of said predetermined areas exceeds a predetermined value.

20. A method as in claim 1, further comprising the step, performed prior to step (a), of:

(f) decomposing said placement into a hierarchial order of groups of cells; and

step (a) comprises routing said groups of cells in parallel.

21. A physical design automation system for optimizing a cell placement for an integrated circuit chip, comprising:

a router for routing said cell placement; and

a computer for performing operations of;

identifying congested areas of said routing;

selectively applying a congestion reduction algorithm only within said congested areas to alter said cell placement in said congested areas; and

computing a cell placement fitness; and

a controller for controlling the computer to repeat performing said operations until said cell placement fitness attains a predetermined value.

22. A system as in claim 21, in which the controller further controls the router to reroute said placement if said fitness is below said predetermined value.

23. A system as in claim 21, in which the router comprises a global router for globally routing said placement.

24. A system as in claim 21, in which:

said placement comprises a plurality of nets of cells; and

the router comprises a plurality of parallel processors for routing said nets in parallel.

25. A system as in claim 21, in which the router divides said placement into a plurality of predetermined areas, and comprises a plurality of parallel processors for routing said predetermined areas in parallel.

26. A system as in claim 21, in which the computer comprises a plurality of parallel processors for applying said congestion reduction algorithm to alter said placement in said congested areas in parallel.

27. A system as in claim 21, in which:

said congestion reduction algorithm comprises relocating selected cells such that routing thereof does not pass through said congested areas; and

the computer comprises a plurality of parallel processors for relocating said selected cells in parallel.

28. A system as in claim 21, in which the computer divides said placement into a plurality of predetermined areas, and comprises a plurality of parallel processors for applying said congestion reduction algorithm to said plurality of predetermined areas in parallel.