Method of anti-fuse repair
First Claim
Patent Images
1. An integrated circuit comprising:
- an anti-fuse having first and second plates separated by a layer of dielectric;
programming circuitry adapted to couple a first potential to the first plate; and
a virtual ground coupled to the second plate for providing a second potential to the second plate, such that a differential voltage between the first and second plates is sufficient to create a conductive path through the dielectric.
8 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.
107 Citations
22 Claims
-
1. An integrated circuit comprising:
-
an anti-fuse having first and second plates separated by a layer of dielectric; programming circuitry adapted to couple a first potential to the first plate; and a virtual ground coupled to the second plate for providing a second potential to the second plate, such that a differential voltage between the first and second plates is sufficient to create a conductive path through the dielectric.
-
-
2. An integrated circuit comprising:
-
an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; and a bias circuit connected to the second conductive plate for coupling the second conductive plate to a ground voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero. - View Dependent Claims (3, 4, 5, 6, 7, 10, 11, 12)
-
-
8. An integrated circuit comprising:
-
an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and
the bias circuit comprises;a transistor having a first connection coupled to the second conductive plate and a second connection coupled to a bias voltage connection to define a current path from the bias voltage connection to the second conductive plate; and a resistor located electrically in the current path between the bias voltage connection to the second conductive plate.
-
-
9. An integrated circuit comprising:
-
an anti-fuse having first and second conductive plates; a layer of oxide fabricated between the first and second conductive plates; anti-fuse logic circuitry connected to the first conductive plate for selectively coupling the first conductive plate to a program voltage level; an external connection connected to the second conductive plate for coupling the second conductive plate to a pre-determined external voltage level during anti-fuse programming, the pre-determined external voltage level being non-zero; a bias circuit connected to the second conductive plate for coupling the second conductive plate to a bias voltage level; and wherein the bias circuit comprises a plurality of transistors connected in series between the second conductive plate and the bias voltage level.
-
-
13. An integrated circuit memory device comprising:
-
an anti-fuse comprising a layer of oxide fabricated between an n-type polysilicon layer and an n-well formed in a substrate; program circuitry connected to the n-type polysilicon layer for providing a program voltage to the n-type polysilicon layer; an external connection coupled to the n-well for providing an external voltage to the n-well; and a bias circuit connected to the n-well for coupling the n-well to a ground voltage. - View Dependent Claims (14, 15, 16, 17)
-
-
18. An integrated circuit memory device comprising:
-
an external connection coupled to an anti-fuse comprising a layer of oxide fabricated between a polysilicon layer and a well formed in a substrate, and a bias circuit connected to the well for coupling the well to a ground voltage; and program circuitry connected to the polysilicon layer for providing a program voltage to the polysilicon layer.
-
-
19. A method of programming an integrated circuit anti-fuse, the anti-fuse comprising first and second conductive plates having a layer of oxide fabricated therebetween, the method comprising the steps of:
-
coupling the first conductive plate to a program voltage; coupling the second conductive plate to an opposite voltage through an external connection to create a current path through the layer of oxide to electrically connect the first and second conductive layers; and coupling the well to zero potential through a bias circuit. - View Dependent Claims (20, 21, 22)
-
Specification