Processing CDMA signals

• US 5,742,595 A
• Filed: 11/16/1995
• Issued: 04/21/1998
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: DSC Communications Corp. (Nokia Corporation)
• Inventors: Bhagalia, Shashikant
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): Yao, Kwang Bin
• Application Number:
  US08/558,675
• Time in Patent Office: 887 Days
• Field of Search: 370/18, 370/320, 370/335, 370/342, 370/488, 370/497, 370/537, 375/200, 375/205, 375/260, 375/267, 375/281, 375/282, 375/287, 375/333, 381/7, 235/454, 379/410
• US Class Current: 370/342
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/7077 Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
• CPC Class Codes: H04B 1/70775 Multi-dwell schemes, i.e. multiple accumulation times
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 2001/70706 using a code tracking loop, e.g. a delay locked loop
• CPC Class Codes: H04B 2201/70702 Intercell-related aspects
• CPC Class Codes: H04B 2201/70706 with means for reducing the peak-to-average power ratio
• CPC Class Codes: H04B 2201/7071 with dynamic control of receiver resources
• CPC Class Codes: H04B 2201/70711 with modular structure
• CPC Class Codes: H04B 2201/709709 Methods of preventing interference
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 41/0226 Mapping or translating multiple network management protocols
• CPC Class Codes: H04L 41/0233 Object-oriented techniques, for representation of network management data, e.g. common object request broker architecture [CORBA]
• CPC Class Codes: H04L 41/08 Configuration management of networks or network elements address allocation H04L61/50
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 43/00 : Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/14 : Multichannel or multilink protocols
• CPC Class Codes: H04L 9/40 : Network security protocols
• CPC Class Codes: H04Q 11/04 : for time-division multiplexing H04Q11/0001 takes precedence
• CPC Class Codes: H04Q 2213/1305 : Software aspects
• CPC Class Codes: H04Q 2213/13093 : Personal computer, PC
• CPC Class Codes: H04Q 2213/13098 : Mobile subscriber
• CPC Class Codes: H04Q 2213/13109 : Initializing, personal profile
• CPC Class Codes: H04Q 2213/1319 : Amplifier, attenuation circuit, echo suppressor
• CPC Class Codes: H04Q 2213/13196 : Connection circuit/link/trunk/junction, bridge, router, gateway
• CPC Class Codes: H04Q 2213/13199 : Modem, modulation
• CPC Class Codes: H04Q 2213/13202 : Network termination [NT]
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13216 : Code signals, frame structure
• CPC Class Codes: H04Q 2213/13292 : Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13296 : Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/13298 : Local loop systems, access network
• CPC Class Codes: H04Q 2213/13299 : Bus
• CPC Class Codes: H04Q 2213/13335 : Simulation, emulation
• CPC Class Codes: H04Q 2213/13376 : Information service, downloading of information, 0800/0900 services
• CPC Class Codes: H04W 52/04 : TPC
• CPC Class Codes: H04W 52/08 : Closed loop power control
• CPC Class Codes: H04W 52/52 : using AGC [Automatic Gain Control] circuits or amplifiers
• CPC Class Codes: H04W 8/205 : Transfer to or from user equipment or user record carrier
• CPC Class Codes: H04W 84/14 : WLL [Wireless Local Loop]; RLL [Radio Local Loop]
• CPC Class Codes: H04W 88/021 : adapted for Wireless Local Loop operation
• CPC Class Codes: H04W 92/08 : between user and terminal device

Abstract

A CDMA signal processing circuit (300) includes a summer circuit (302) that receives a plurality of CDMA signals from a plurality of channels (304). The summer circuit (302) combines the plurality of CDMA signals according to a power magnitude value and power direction value associated with each CDMA signal. The summer circuit (302) generates a summed signal (306) that is applied to a clipping circuit (308). The clipping circuit (308) removes a portion of the summed signal (306) outside a desired threshold range and generates a clipped signal (310) therefrom. Digital to analog processing circuits (312 and 314) convert the clipped signal (310) into a half width encoded format. Digital to analog processing circuits (312 and 314) transform the half width encoded clipped signal into analog I and Q signals, respectively. The analog I and Q signals are applied to corresponding filters (316 and 318) prior to transmission.

Claims

1. A method of processing CDMA signals, comprising the steps of:

performing a spreading function on CDMA signals from a plurality of channels;

combining the CDMA signals of the plurality of channels to create a summed signal;

removing a portion of the summed signal above and below a desired threshold range to create a clipped signal wherein the CDMA signals have a disable value, a power magnitude value, and a power direction value used in determining the summed signal.

2. The method of claim 1, wherein the power magnitude value has a first level representing an on-hook condition and a second level value representing an off-hook condition.

3. The method of claim 1, wherein the digital summed signal ranges in value from -64 to +64 in response to a disabled value of zero, a power magnitude value ranging from a low power value of 1 to a high power value of 4, and a power direction value of positive or negative.

4. A method of processing CDMA signals, comprising the steps of:

performing a spreading function on CDMA signals from a plurality of channels;

combining the CDMA signals of the plurality of channels to create a summed signal;

converting the summed signal into two separate data channels for modulating a radio frequency carrier transmission signal, each of the two separate data channels carrying information in a half-width pulse configuration, wherein a first half of the pulse contains valid information and a second half of the pulse has a return to zero format;

removing a portion of the summed signal above and below desired threshold range to create a clipped signal, wherein the CDMA signals have a disable value, a power magnitude value, and a power direction value used in determining the summed signal.

5. The method of claim 4, wherein the power magnitude value has a first level representing an on-hook condition and a second level representing an off-hook condition.

6. The method of claim 4, wherein the summed signal ranges in value from -64 to +64 in response to a disabled value of zero, a power magnitude value of 1 and 4, and a power direction value of positive or negative.

7. An apparatus for processing CDMA signals, comprising:

a summer circuit operable to combine CDMA signals from a plurality of channels, the summer circuit operable to generate a summed signal therefrom;

a clipping circuit operable to remove a portion of the summed signal above and below a desired threshold range, the clipping circuit operable to generate a clipped signal therefrom;

a digital to analog processing circuit operable to convert the clipped signal into a half width encoded format, the half width encoded format having information contained in a first half of a signal pulse and no information in a second half of the signal pulse, the digital to analog processing circuit operable to convert the clipped signal in the half width encoded format to an analog signal;

a filter operable to reduce inter-symbol interference in the analog signal, wherein the clipping circuit removes the portion of the summed signal sufficient to prevent noise producing sidebands from appearing on the clipped output signal, wherein each CDMA signal has a disable value, a power magnitude value, or a power direction value for use in determining the summed signal, the summed signal ranging in value from -64 to +64 in response to a disabled value of zero, a power magnitude value of 1 and 4, and a power direction value of positive and negative, the desired threshold range being approximately one half the total range of the summed signal.