Multiplex ATM/STM converter for structured data

• US 5,742,600 A
• Filed: 06/05/1996
• Issued: 04/21/1998
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: NEC Corporation
• Inventors: Nishihara, Motoo
• Primary Examiner(s): NGUYEN, CHAU T
• Application Number:
  US08/655,216
• Time in Patent Office: 685 Days
• Field of Search: 370/517, 370/382, 370/389, 370/392, 370/395, 370/412, 370/396, 370/397, 370/399, 370/378, 370/379, 370/374, 370/363, 370/516, 370/409, 370/474, 375/371, 375/372
• US Class Current: 370/395.6
• CPC Class Codes: H04J 2203/0089 Multiplexing, e.g. coding, scrambling, SONET
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

The disclosed device allows de-ceiling of ATM cells in structured data transmission according to ITU-Telecommunication Recommendation I. 363, reproduction of a plurality of STM frames represented at a speed of 64 kbps×n (n=any natural number), and moreover, discloses an architecture that allows a minimum of the buffer amount due to the de-ceiling. The ATM/STM converter according to the present invention includes an AAL1 processor 101, a common buffer section 102 that stores ATM cell payloads using link-list queues and in which a pointer within that link list is also stored, a write controller 103 that manages write addresses to the common buffer section, a read controller 105 that manages read addresses to the common buffer section, an empty cell address FIFO section 104 that manages a list of empty cell addresses within the common buffer section, a buffer initialization controller 107 that initializes the common buffer section, a frame position detector 108 that monitors the frame position of STM signals, and a CM section 106 that relates channel arrangement on the STM side with VP on the ATM side.

Claims

1. A multiplex ATM/STM converter for structured data which is an ATM/STM conversion circuit that converts back to original STM signals ATM cells by which information is transmitted in cell units for each channel of STM signals having a plurality of channels time-division multiplexed into frame cycles;

and comprising;

an ATM adaptation layer 1 (AAL1) processor (101) that inputs said ATM cells, subjects these ATM cells to SAR/CS layer processing according to structured data transmission protocol of ITU-Telecommunication Recommendation I. 363, and as one result of this processing, extracts virtual path identifiers and frame positions of STM frames and outputs said ATM cells;

cell buffer means that stores said ATM cells by each virtual path to absorb cell delay variation (CDV) of said ATM cells;

a write controller within said cell buffer means which, when establishing regions as cell blocks for storing each virtual path, controls cell block addresses for writing to said cell buffer means ATM cells having virtual path numbers extracted by said AAL1 processor;

a control memory section in which is stored the channel arrangement of virtual paths of ATM cells to STM frames, and from which is read, in accordance with frame conditions of the STM network, information designating a virtual path to be read next from said cell buffer means;

a read controller that manages read-out addresses to said cell buffer means and reads from said cell buffer means virtual paths designated by output of said control memory section; and

a buffer initialization controller that inputs signals that notify of generation of writing and readout from said write controller and read controller, respectively, and monitors the amount of information stored in said cell buffer means, and which executes buffer initialization processing when said amount of information satisfies prescribed conditions;

wherein said cell buffer means comprises a plurality of queues for storing payloads of ATM cells received from said AAL1 processor for each virtual path, and moreover, is structured as a common buffer in which buffer amounts of cell blocks making up each queue are mutually and independently set such that the sum total of buffer amounts of all queues equals a prescribed value determined depending on the transmission path capacity.

2. A device according to claim 1 wherein, if the virtual path identifier of the virtual path stored in that queue is k, the frame length of virtual path k is F_k, and the ratio of cell delay variation T to frame cycle T_f (T/T_f) is n, the buffer amount of each of the queues is set to equal 2nF_k.

3. A device according to claim 2 wherein, if cell delay variation of that ATM network is T, the sum total of buffer amounts is set to equal 2T times the transmission path capacity.

4. A device according to claim 1 wherein said plurality of queues make up a link list.

5. A device according to claim 4 wherein said common buffer comprises a cell buffer section, a pointer buffer section, a latch section, and a counter;

said cell buffer section comprises queues corresponding are each for each virtual path, and each individual cell block of a queue stores a payload of an individual ATM cell;

the address of information stored in a cell block is designated by two types of addresses;

a cell block address designating the cell block and an offset address designating stored position within each individual cell block;

said pointer buffer section stores pointers of queues made up a link list structure within said cell buffer section, said pointers designating the cell block address of a next cell block of cell blocks constituting that queue;

said latch section latches cell block addresses;

said counter counts to 46 or 47 depending on whether input ATM cells are of P format or non-P format, respectively, and designates said offset address.

6. A device according to claim 1 wherein said read controller comprises a head register section and a down-counter, said head register section stores cell block address for reading corresponding virtual path, said down-counter generates offset addresses for reading and counts down to 0 from a value of 46 or 47 depending on whether each cell block read out by channel on the STM network side is of P format or non-P format.

7. A device according to claim 2 wherein said buffer initialization controller comprises a frame counter, queue length up/down counter, and comparison section;

said frame counter monitors output of said control memory section in frame cycle intervals by virtual path (k) and calculates frame length (F_k);

multiplies this frame length by ratio n to calculate first buffer threshold value Th₁,k by virtual path, and further, doubles Th₁,k to calculate second buffer threshold value Th₂,k by virtual path;

said queue length up/down counter inputs signals from write controller and read controller notifying of occurrence of write and read, respectively, and calculates queue length by virtual path within said cell buffer for each cell block; and

said comparison section compares queue length outputted by said queue length up/down counter with the output of said frame counter, and said buffer initialization controller, for each respective virtual path (k), after resetting a queue when that queue length is 0 or Th₂,k, generates a buffer initialization signal that directs said write controller and said read controller to perform write while halting read-out of that queue until the queue length reaches Th₁,k, and generates a buffer initialization process completion signal to resume reading when queue length of that queue reaches Th₁,k.