Receiving circuitry for receiving serially transmitted encoded information

• US 5,742,644 A
• Filed: 02/07/1995
• Issued: 04/21/1998
• Est. Priority Date: 03/12/1992
• Status: Expired due to Term

• Current Assignee: NTP Incorporated
• Original Assignee: NTP Incorporated
• Inventors: Campana, Thomas J. Jr.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHAYOUR, MOHAMMAD H
• Application Number:
  US08/385,312
• Time in Patent Office: 1,169 Days
• Field of Search: 370/100.1, 370/105.1, 370/105.4, 370/503, 370/506, 370/516, 375/316
• US Class Current: 375/316
• CPC Class Codes: H04B 7/10 Polarisation diversity; Directional diversity
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/02 by diversity reception
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 84/042 Public Land Mobile systems, e.g. cellular systems

Abstract

The present invention provides reconstruction and resynchronization of wireless serial transmissions which are subject to fading causing erroneous uncorrectable bit errors exceeding the error correction code correction capacity present in frames of digitally encoded data. Valid data is reconstructed in frames which are determined to contain at least one erroneous uncorrectable bit exceeding the bit error correction capacity of the error correction code therein which have all erroneous uncorrectable bits within the error correction code bit held. A synchronization marker is transmitted with each frame group which does not represent any valid data in a frame. Detection of the synchronization marker by a digital signal processor after at least one frame is determined to contain at least one erroneous uncorrectable bit, which is indicative of a loss of synchronism of the receiving circuitry clock, resynchronizes the clock of a processor of the receiving circuitry. After resynchronization of the clock, frames beginning with the at least one frame containing the at least one erroneous uncorrectable bit indicative of the loss of clock synchronism to the frames in the frame group containing the synchronization marker are reconstructed to recover a data in frames which do not contain at least one erroneous uncorrectable bit and, as described above, to recover valid data bits in frames containing at least one erroneous uncorrectable bit. Finally, frames transmitted after the detected synchronization marker are processed synchronously including reconstruction or resynchronization as described above.

Claims

1. A process for recovering faded information in a plurality of frames of information wirelessly transmitted with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with the plurality of frames of information with the plurality of frames of information including a plurality of bits encoding error correction code and a plurality of other bits comprising:

receiving the radio frequency carrier, detecting the bits of the transmitted frames modulated on the subcarrier and storing the detected bits;

processing the stored bits of the frames with the error correction code therein to determine if the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein;

processing the bits of any frames which contain at least one erroneous uncorrectable bit to determine if the other bits of the at least one frame are valid other bits; and

storing the valid other bits of each frame.

2. A process in accordance with claim 1 further comprising:

processing the plurality of bits of each frame determined to contain at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the error correction code, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit totally contain the at least one erroneous uncorrectable bit, storing as valid other bits each of the other bits of each frame determined to contain the at least one erroneous uncorrectable bit totally in the bits of the error correction code.

3. A process in accordance with claim 1 further comprising:

processing the plurality of bits of each frame determined to contain the at least one erroneous uncorrectable bit to determine if the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, storing as invalid other bits each of the other bits of each frame determined to contain the at least one erroneous uncorrectable bit not totally in the bits of the error correction code.

4. A process in accordance with claim 2 further comprising:

processing the plurality of bits of each frame determined to contain the at least one erroneous uncorrectable bit to determine if the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, storing as invalid other bits each of the other bits of each frame determined to contain the at least one erroneous uncorrectable bit not totally in the bits of the error correction code.

5. A process in accordance with claim 1 wherein the processing of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

storing the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

6. A process in accordance with claim 2 wherein the processing of the stored bits of any of the frames which contain the at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

storing the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

7. A process in accordance with claim 3 wherein the processing of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

storing the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

8. A process in accordance with claim 4 wherein the processing of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

storing the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

9. A process in accordance with claim 5 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

10. A process in accordance with claim 6 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

11. A process in accordance with claim 7 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

12. A process in accordance with claim 8 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

13. A process in accordance with claim 1 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

14. A process in accordance with claim 2 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

15. A process in accordance with claim 3 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

16. A process in accordance with claim 4 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

17. A process in accordance with claim 5 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

18. A process in accordance with claim 6 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

19. A process in accordance with claim 7 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

20. A process in accordance with claim 8 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

21. A process in accordance with claim 9 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

22. A process in accordance with claim 10 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

23. A process in accordance with claim 11 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

24. A process in accordance with claim 12 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

25. A process in accordance with claim 1 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

26. A process in accordance with claim 25 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

27. A process in accordance with claim 26 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

28. A process in accordance with claim 27 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

29. A process in accordance with claim 1 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

30. A process in accordance with claim 29 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

31. A process in accordance with claim 30 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

32. A process in accordance with claim 31 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

33. A process in accordance with claim 2 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

34. A process in accordance with claim 33 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

35. A process in accordance with claim 34 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

36. A process in accordance with claim 35 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

37. A process in accordance with claim 2 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

38. A process in accordance with claim 37 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

39. A process in accordance with claim 38 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

40. A process in accordance with claim 39 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

41. A process in accordance with claim 3 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

42. A process in accordance with claim 41 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

43. A process in accordance with claim 42 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

44. A process in accordance with claim 43 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

45. A process in accordance with claim 3 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

46. A process in accordance with claim 45 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

47. A process in accordance with claim 46 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

48. A process in accordance with claim 47 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

49. A process in accordance with claim 5 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

50. A process in accordance with claim 49 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

51. A process in accordance with claim 50 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

52. A process in accordance with claim 51 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

53. A process in accordance with claim 5 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

54. A process in accordance with claim 53 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

55. A process in accordance with claim 54 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

56. A process in accordance with claim 55 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

57. A process in accordance with claim 13 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

58. A process in accordance with claim 57 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

59. A process in accordance with claim 58 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

60. A process in accordance with claim 59 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

61. A process in accordance with claim 13 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

62. A process in accordance with claim 61 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

63. A process in accordance with claim 62 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

64. A process in accordance with claim 63 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

65. A process for resynchronizing reception of a plurality of frames of information wirelessly transmitted with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with at least one identification frame group which identifies receiving circuitry to receive the information followed by at least one data frame group, each identification frame group comprising at least one frame containing bits identifying the receiving circuitry to receive the radio frequency carrier, a plurality of bits of error correction code in each frame, and synchronization information for originally synchronizing a clock of the receiving circuitry with each data frame group comprising a plurality of frames each including a plurality of bits of error correction code and a plurality of bits of data, and a synchronization marker comprising a plurality of bits for resynchronizing the clock of the receiving circuitry comprising:

receiving the radio frequency carrier, detecting the bits of the at least one identification frame group and the at least one data frame group modulated on the subcarrier, originally synchronizing the clock in response to the synchronization information and storing the detected bits of the at least one frame of the at least one identification frame and the frames of the at least one data frame group;

processing the stored bits of at least one frame with the error correction code therein to determine if the stored bits of the at least one frame contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein which is representative of the clock of the receiving circuitry requiring resynchronization; and

searching the stored bits transmitted after the stored bits of the at least one processed frame containing the at least one erroneous uncorrectable bit to detect a synchronization marker and using the detected synchronization marker to resynchronize the clock.

66. A process in accordance with claim 65 further comprising:

processing the stored bits of a plurality of frames with the error correction code therein to determine if the stored bits of the plurality of frames each contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein which is representative of the clock of the receiving circuitry requiring resynchronization; and

searching the stored bits transmitted after the stored bits of the plurality of frames each containing the at least one uncorrectable erroneous bit to detect the synchronization marker and using the detected synchronization marker to resynchronize the clock.

67. A process in accordance with claim 65 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, processing the bits of frames in at least one frame group transmitted after the frame group containing the detected synchronization marker to determine if an address encoded within the at least one frame group transmitted after the frame group containing the detected synchronization marker identifies an address of a frame group contained within the transmission of the plurality of frames of information and when the address is an address of a frame group within the wireless transmission of the plurality of frames of information processing the frames which were transmitted after the detected synchronization marker as part of the transmission of the plurality of frames of information and when the address is not an address within the wireless transmission of the plurality of frames of information ceasing processing the transmission of the plurality of frames of information.

68. A process in accordance with claim 65 further comprising:

after resynchronization of the clock, reconstructing the bits of frames within the frame group containing the detected synchronization marker to store data bits of those frames within the frame group containing the detected synchronization marker which contain only valid bits outside a field of the error correction code bits and in those frames which do not contain only valid bits outside the field of the error correction code bits storing an error marker for the frame where the invalid bits are found.

69. A process in accordance with claim 65 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, processing a frame group address of the frame group containing the detected synchronization marker and a frame group address of the frame group containing at least one frame containing the at least one erroneous uncorrectable bit which is representative of the clock requiring resynchronization to identify frames to be reconstructed; and

reconstructing the identified frames to identify those frames which contain only valid bits outside a field of the error correction code and storing the valid bits and to identify those frames which contain any invalid bits outside the field of the error correction code, and storing an error marker for any frame where invalid bits are found.

70. A process in accordance with claim 66 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, processing the bits of frames in at least one frame group transmitted after the frame group containing the detected synchronization marker to determine if an address encoded within the at least one frame group transmitted after the frame group containing the detected synchronization marker identifies an address of a frame group contained within the transmission of the plurality of frames of information and when the address is an address of a frame group within the wireless transmission of the plurality of frames of information processing the frames which were transmitted after the detected synchronization marker as part of the transmission of the plurality of frames of information and when the address is not an address within the wireless transmission of the plurality of frames of information ceasing processing the transmission of the plurality of frames of information.

71. A process in accordance with claim 66 further comprising:

after resynchronization of the clock reconstructing the bits of frames within the frame group containing the detected synchronization marker to store data bits of those frames within the frame group containing the detected synchronization marker which contain only valid bits outside a field of the error correction code bits and in those frames which do not contain only valid bits outside the field of the error correction code bits storing an error marker for any frame where invalid data bits are found.

72. A process in accordance with claim 66 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, processing a frame group address of the frame group containing the detected synchronization marker and a frame group address of the frame group containing a plurality of frames containing the at least one erroneous uncorrectable bit which is representative of the clock requiring resynchronization to identify frames to be reconstructed; and

reconstructing the identified frames to identify those frames which contain only valid bits outside a field of the error correction code and those frames which contain any invalid bits outside the field of the error correction code and storing the valid bits and storing an error marker for any frame where invalid bits are found.

73. A process in accordance with claim 67 further comprising:

processing the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, storing bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

74. A process in accordance with claim 68 further comprising:

reprocessing the bits of the frames within the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein, storing bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame containing the at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

75. A process in accordance with claim 69 further comprising:

reprocessing the bits of the frames to be reconstructed with the error correction code therein to determine if the plurality of bits of the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein, storing bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames transmitted before the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame containing the at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

76. A process in accordance with claim 70 further comprising:

processing the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, storing bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

77. A process in accordance with claim 71 further comprising:

reprocessing the bits of the frames within the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein, storing the bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame containing the at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

78. A process in accordance with claim 72 further comprising:

reprocessing the bits of the frames to be reconstructed with the error correction code therein to determine if the plurality of bits of the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein, storing bits outside a field of the error correction code as valid bits and discarding the bits of the error correction code of frames transmitted before the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processing the plurality of bits of each frame containing the at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit storing bits outside the field of the error correction code as valid bits and discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit storing an error marker for any frame where invalid bits are found.

79. A process in accordance with claim 65 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

80. A process in accordance with claim 79 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

81. A process in accordance with claim 80 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

82. A process in accordance with claim 81 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

83. A process in accordance with claim 65 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

84. A process in accordance with claim 83 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

85. A process in accordance with claim 84 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

86. A process in accordance with claim 85 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

87. A process in accordance with claim 66 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

88. A process in accordance with claim 87 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

89. A process in accordance with claim 88 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

90. A process in accordance with claim 89 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

91. A process in accordance with claim 66 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

92. A process in accordance with claim 91 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

93. A process in accordance with claim 92 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

94. A process in accordance with claim 93 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

95. A process in accordance with claim 67 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

96. A process in accordance with claim 95 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

97. A process in accordance with claim 96 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

98. A process in accordance with claim 97 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

99. A process in accordance with claim 67 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

100. A process in accordance with claim 99 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

101. A process in accordance with claim 100 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

102. A process in accordance with claim 101 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

103. A process in accordance with claim 68 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

104. A process in accordance with claim 103 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

105. A process in accordance with claim 104 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

106. A process in accordance with claim 105 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

107. A process in accordance with claim 68 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

108. A process in accordance with claim 107 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

109. A process in accordance with claim 108 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

110. A process in accordance with claim 109 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

111. A process in accordance with claim 69 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

112. A process in accordance with claim 111 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

113. A process in accordance with claim 112 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

114. A process in accordance with claim 113 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

115. A process in accordance with claim 69 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

116. A process in accordance with claim 115 further comprising:

processing detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substituting for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

117. A process in accordance with claim 116 wherein:

the processing of the detected individual cycles of the subcarrier includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

118. A process in accordance with claim 117 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

119. Receiving circuitry for recovering faded information in a plurality of frames of information wirelessly transmitted with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with the plurality of frames of information with the plurality of frames of information with each frame including a plurality of bits encoding error correction code and a plurality of other bits comprising:

an antenna for receiving the radio frequency carrier, at least one processor, coupled to the antenna, for detecting the bits of the transmitted frames modulated on the subcarrier and a memory, coupled to the at least one processor, for storing the detected bits and the at least one processor processing the stored bits of the frames with the error correction code therein to determine if the frames contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein, processing the bits of any frames which contain at least one erroneous uncorrectable bit to determine if the other bits of the at least one frame are valid other bits, and controlling storing of the valid other bits of each frame in the memory.

120. Receiving circuitry in accordance with claim 119 wherein:

the at least one processor processes the plurality of bits of each frame determined to contain at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the error correction code, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit totally contain the at least one erroneous uncorrectable bit, the at least one processor controls storing in the memory as valid other bits each of the other bits of each frame determined to contain the at least one erroneous uncorrectable bit totally in the bits of the error correction code.

121. Receiving circuitry in accordance with claim 119 wherein:

the at least one processor processes the plurality of bits of each frame determined to contain the at least one erroneous uncorrectable bit to determine if the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, the at least one processor controls storing in the memory as invalid other bits each of the other bits of each frame determined to contain the at least one erroneous uncorrectable bit not totally in the bits of the error correction code.

122. Receiving circuitry in accordance with claim 120 wherein:

the at least one processor processes the plurality of bits of each frame determined to contain the at least one erroneous uncorrectable bit to determine if the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, and upon determination that the bits of the error correction code of each frame containing at least one erroneous uncorrectable bit do not totally contain the at least one erroneous uncorrectable bit, the at least one processor controls storing in the memory an error marker for each frame determined to contain the at least one erroneous uncorrectable bit not totally in the bits of the error correction code.

123. Receiving circuitry in accordance with claim 119 wherein the processing by the at least one processor of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

controls storing in the memory the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

124. Receiving circuitry in accordance with claim 120 wherein the processing by the at least one processor of the stored bits of any of the frames which contain the at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

controls storing in the memory the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

125. Receiving circuitry in accordance with claim 121 wherein the processing by the at least one processor of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

controls storing in the memory the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

126. Receiving circuitry in accordance with claim 122 wherein the processing by the at least one processor of the stored bits of any of the frames which contain at least one erroneous uncorrectable bit to determine if the frames contain only valid other bits comprises:

processing the bits of the error correction code contained in each frame which contains at least one erroneous uncorrectable bit to search for a bit pattern of the erroneous uncorrectable bits totally within the bits of the error correction code; and

controls storing in the memory the other bits as valid other bits when the bit pattern of erroneous uncorrectable bits is detected as being totally within the bits of the error correction code.

127. Receiving circuitry in accordance with claim 123 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

128. Receiving circuitry in accordance with claim 124 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

129. Receiving circuitry in accordance with claim 125 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

130. Receiving circuitry in accordance with claim 125 wherein:

the bit pattern is a number of successive bits having an identical numeric value of either zero or one with the number being at least one greater than a number of bits which may be corrected with the error correction code in a frame.

131. Receiving circuitry in accordance with claim 119 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

132. Receiving circuitry in accordance with claim 120 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

133. Receiving circuitry in accordance with claim 121 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

134. Receiving circuitry in accordance with claim 122 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

135. Receiving circuitry in accordance with claim 123 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

136. Receiving circuitry in accordance with claim 124 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

137. Receiving circuitry in accordance with claim 125 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

138. Receiving circuitry in accordance with claim 126 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

139. Receiving circuitry in accordance with claim 127 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

140. Receiving circuitry in accordance with claim 128 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

141. Receiving circuitry in accordance with claim 129 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

142. Receiving circuitry in accordance with claim 130 wherein:

the plurality of frames comprise at least one identification frame and at least one data frame with the other bits of each identification frame comprising a plurality of bits encoding at least identification information of the receiving circuitry and the other bits of each data frame comprising a plurality of bits encoding data.

143. Receiving circuitry in accordance with claim 119 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

144. Receiving circuitry in accordance with claim 143 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

145. Receiving circuitry in accordance with claim 144 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

146. Receiving circuitry in accordance with claim 145 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

147. A system in accordance with claim 119 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

148. Receiving circuitry in accordance with claim 147 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

149. Receiving circuitry in accordance with claim 148 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

150. Receiving circuitry in accordance with claim 149 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

151. Receiving circuitry in accordance with claim 120 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

152. Receiving circuitry in accordance with claim 151 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

153. Receiving circuitry in accordance with claim 152 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

154. Receiving circuitry in accordance with claim 153 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

155. Receiving circuitry in accordance with claim 120 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

156. Receiving circuitry in accordance with claim 155 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

157. Receiving circuitry in accordance with claim 156 wherein:

the processing of the detected individual cycles of the subcarrier with the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

158. Receiving circuitry in accordance with claim 157 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

159. Receiving circuitry in accordance with claim 121 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

160. Receiving circuitry in accordance with claim 159 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

161. Receiving circuitry in accordance with claim 160 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

162. Receiving circuitry in accordance with claim 161 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

163. Receiving circuitry in accordance with claim 121 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

164. Receiving circuitry in accordance with claim 163 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

165. Receiving circuitry in accordance with claim 164 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

166. Receiving circuitry in accordance with claim 165 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

167. Receiving circuitry in accordance with claim 123 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

168. Receiving circuitry in accordance with claim 167 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

169. Receiving circuitry in accordance with claim 168 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

170. Receiving circuitry in accordance with claim 169 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

171. Receiving circuitry in accordance with claim 123 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

172. Receiving circuitry in accordance with claim 171 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

173. Receiving circuitry in accordance with claim 172 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

174. Receiving circuitry in accordance with claim 173 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

175. Receiving circuitry in accordance with claim 131 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

176. Receiving circuitry in accordance with claim 175 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

177. Receiving circuitry in accordance with claim 176 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

178. Receiving circuitry in accordance with claim 177 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

179. Receiving circuitry in accordance with claim 131 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

180. Receiving circuitry in accordance with claim 179 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

181. Receiving circuitry in accordance with claim 180 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

182. Receiving circuitry in accordance with claim 181 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

183. Receiving circuitry for resynchronizing reception of a plurality of frames of information wirelessly transmitted with a radio frequency carrier modulated with a subcarrier with the subcarrier being modulated with at least one identification frame group which identifies the receiving circuitry to receive the information followed by at least one data frame group with each identification frame group comprising at least one frame containing bits identifying the receiving circuitry to receive the radio frequency carrier, a plurality of bits of error correction code in each frame, and synchronization information for originally synchronizing a clock of the receiving circuitry with each data frame group comprising a plurality of frames each including a plurality of bits of error correction code and a plurality of bits of data, and synchronization marker comprised of a plurality of bits for resynchronizing the clock of the receiving circuitry comprising:

an antenna for receiving the radio frequency carrier, at least one processor, coupled to the antenna, for detecting the bits of the at least one identification frame group and the at least one data frame group modulated on the subcarrier, a memory, coupled to the at least one processor, for storing the detected bits of the frames of the at least one identification frame and the frames of the at least one data frame group and the at least one processor processing the stored bits of at least one frame with the error correction code therein to determine when the stored bits of the at least one frame contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code therein which is representative of the clock requiring resynchronization, and searching the stored bits transmitted after the stored bits of the at least one processed frame containing the at least one erroneous uncorrectable bit to detect a synchronization marker and in response to the detected synchronization marker resynchronizing the clock.

184. Receiving circuitry in accordance with claim 183 wherein:

the at least one processor processes the stored bits of a plurality of frames with the error correction code therein to determine if the stored bits of the plurality of frames each contain at least one uncorrectable erroneous bit which cannot be corrected with the error correction code therein which is representative of the clock requiring resynchronization, and searches the stored bits transmitted after the stored bits of the plurality of frames containing the at least one erroneous uncorrectable bit to detect the synchronization marker and in response to the detected synchronization marker resynchronizing the clock.

185. Receiving circuitry in accordance with claim 183 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, the at least one processor processes the bits of frames in at least one frame group transmitted after the frame group containing the detected synchronization marker to determine if an address encoded within the at least one frame group transmitted after the frame group containing the detected synchronization marker identifies an address of a frame group contained within the transmission of the plurality of frames of information and when the address is an address of a frame group within the wireless transmission of the plurality of frames of information processes the frames which were transmitted after the detected synchronization marker as part of the transmission of the plurality of frames of information and when the address is not an address within the wireless transmission of the plurality of frames of information ceases processing the transmission of the plurality of frames of information.

186. Receiving circuitry in accordance with claim 183 further comprising:

after resynchronization of the clock, the at least one processor reconstructs the bits of frames within the frame group containing the detected synchronization marker to store data bits of those frames within the frame group containing the detected synchronization marker which contain only valid bits outside a field of the error correction code bits and in those frames which do not contain only valid bits outside the field of the error correction code bits controls storing in the memory an error marker for the frames where the invalid bits are found.

187. Receiving circuitry in accordance with claim 183 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, the at least one processor processes a frame group address of the frame group containing the detected synchronization marker and a frame group address of the frame group containing at least one frame containing the at least one erroneous uncorrectable bit which is representative of the clock circuitry requiring resynchronization to identify frames to be reconstructed and reconstructs the identified frames to identify those frames which contain only valid bits outside a field of the error correction code and controls storing in the memory of the valid bits and in those identified frames which contain any invalid bits outside the field of the error correction code, controls storing in the memory an error marker for those frames where invalid bits are found.

188. Receiving circuitry in accordance with claim 184 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, the at least one processor processes the bits of frames in at least one frame group transmitted after the frame group containing the detected synchronization marker to determine if an address encoded within the at least one frame group transmitted after the frame group containing the detected synchronization marker identifies an address of a frame group contained within the transmission of the plurality of frames of information and when the address is an address of a frame group within the wireless transmission of the plurality of frames of information processes the frames which were transmitted after the detected synchronization marker as part of the transmission of the plurality of frames of information and when the address is not an address within the wireless transmission of the plurality of frames of information ceases processing the transmission of the plurality of frames of information.

189. Receiving circuitry in accordance with claim 184 further comprising:

after resynchronization of the clock, the at least one processor reconstructs the bits of frames within the frame group containing the detected synchronization marker to identify those frames within the frame group containing the detected synchronization marker which contain only valid bits outside a field of the error correction code bits and those frames which do not contain only valid bits outside the field of the error correction code bits, controls storing in the memory the valid bits and controls storing in the memory an error marker for those frames where invalid data bits are found.

190. Receiving circuitry in accordance with claim 184 further comprising:

each frame group containing a frame group address comprised of a plurality of bits which identify a unique address of the frame group within the plurality of frames of wirelessly transmitted information; and

after resynchronization of the clock, the at least one processor processes a frame group address of the frame group containing the detected synchronization marker and a frame group address of the frame group containing a plurality of frames containing the at least one erroneous uncorrectable bit which is representative of the clock circuitry requiring resynchronization to identify frames to be reconstructed and reconstructs the identified frames to identify those identified frames which contain only valid bits outside a field of the error correction code and those identified frames which contain any invalid bits outside the field of the error correction code, controls storing in the memory the valid bits and controls storing in the memory an error marker for those frames where invalid bits are found.

191. Receiving circuitry in accordance with claim 185 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bits are found.

192. Receiving circuitry in accordance with claim 186 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bits are found.

193. Receiving circuitry in accordance with claim 187 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bits are found.

194. Receiving circuitry in accordance with claim 188 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bits are found.

195. Receiving circuitry in accordance with claim 189 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bit are found.

196. Receiving circuitry in accordance with claim 190 wherein:

the at least one processor processes the bits of the frames within the at least one frame group transmitted after the frame group containing the detected synchronization marker with the error correction code therein to determine if the plurality of bits of the frames therein contain at least one erroneous uncorrectable bit which cannot be corrected with the error correction code, controls storing in the memory bits outside a field of the error correction code as valid bits and controls discarding the bits of the error correction code of frames transmitted after the frame group containing the detected synchronization marker which do not contain any erroneous uncorrectable bits and processes the plurality of bits of each frame transmitted after the synchronization marker containing at least one erroneous uncorrectable bit to determine if the at least one erroneous uncorrectable bit is contained totally in the bits of the field of the error correction code, and upon determination that the bits of the error correction code field totally contain the at least one erroneous uncorrectable bit controls storing in the memory bits outside the field of the error correction code as valid bits and controls discarding the bits of the error correction code of each frame containing the at least one erroneous uncorrectable bit totally in the bits of the error correction code and upon determination that the bits of the error correction code do not totally contain the at least one erroneous uncorrectable bit causes storing in the memory an error marker for those frames where invalid bits are found.

197. Receiving circuitry in accordance with claim 183 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

198. Receiving circuitry in accordance with claim 197 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

199. Receiving circuitry in accordance with claim 198 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

200. Receiving circuitry in accordance with claim 199 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

201. Receiving circuitry in accordance with claim 183 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

202. Receiving circuitry in accordance with claim 201 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

203. Receiving circuitry in accordance with claim 202 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

204. Receiving circuitry in accordance with claim 203 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

205. Receiving circuitry in accordance with claim 184 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

206. Receiving circuitry in accordance with claim 205 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

207. Receiving circuitry in accordance with claim 206 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

208. Receiving circuitry in accordance with claim 207 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

209. Receiving circuitry in accordance with claim 184 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

210. Receiving circuitry in accordance with claim 209 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

211. Receiving circuitry in accordance with claim 210 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

212. Receiving circuitry in accordance with claim 211 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

213. Receiving circuitry in accordance with claim 185 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

214. Receiving circuitry in accordance with claim 213 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

215. Receiving circuitry in accordance with claim 214 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

216. Receiving circuitry in accordance with claim 215 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

217. Receiving circuitry in accordance with claim 185 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

218. Receiving circuitry in accordance with claim 217 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

219. Receiving circuitry in accordance with claim 218 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

220. Receiving circuitry in accordance with claim 219 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

221. Receiving circuitry in accordance with claim 186 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

222. Receiving circuitry in accordance with claim 221 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

223. Receiving circuitry in accordance with claim 222 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

224. Receiving circuitry in accordance with claim 223 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

225. Receiving circuitry in accordance with claim 186 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

226. Receiving circuitry in accordance with claim 225 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

227. Receiving circuitry in accordance with claim 226 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

228. Receiving circuitry in accordance with claim 227 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

229. Receiving circuitry in accordance with claim 187 wherein:

cycles of the subcarrier are modulated with pulse width modulation with a width of parts of the subcarrier being modulated with at least one bit of the frames of the information.

230. Receiving circuitry in accordance with claim 229 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically compares each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding at least one bit of the frames of the information.

231. Receiving circuitry in accordance with claim 230 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

232. Receiving circuitry in accordance with claim 231 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

233. Receiving circuitry in accordance with claim 187 wherein:

cycles of the subcarrier are modulated with bits encoding the plurality of frames of information with each cycle of the subcarrier being modulated by the bits at a plurality of separated angular positions.

234. Receiving circuitry in accordance with claim 233 wherein:

the at least one processor processes detected individual cycles of the subcarrier to calculate an integral of at least one selected modulated part of each of the individual cycles, numerically comparing each of the calculated integrals with a plurality of stored numerical ranges which ranges each represent one of a plurality of possible numerical values that the selected part may encode to identify a stored range numerically including the calculated integral and substitutes for the at least one selected part of each of the cycles the one of the plurality of numerical values representative of the identified stored range including the calculated integral with each numerical value encoding one bit of the frames of the information.

235. Receiving circuitry in accordance with claim 234 wherein:

the processing of the detected individual cycles of the subcarrier by the at least one processor includes calculating the integral by taking a plurality of samples of each selected modulated part of each of the individual cycles with each sample having a numerical value and each sample is compared with a range of numerical values representing a valid sample which should be included within the calculation of the integral and when the comparison reveals that the sample value is outside the range of numerical values, the compared sample value is replaced with a value which is a function of the sample values adjacent the sample value which is replaced.

236. Receiving circuity in accordance with claim 235 wherein:

the compared sample value is replaced with a value which is an average of at least one sample value which precedes the compared sample value and at least one sample value which succeeds the compared sample value.

237. A process for resynchronizing reception of a plurality of frames of information transmitted with a radio frequency carrier with the plurality of frames of information including at least one frame including synchronization information for originally synchronizing a clock of receiving circuitry and at least one frame including a synchronization marker comprised of a plurality of bits comprising:

in response to the synchronization information synchronizing the clock of the receiving circuitry;

detecting loss of synchronization of the clock of the receiving circuitry;

in response to the detection of the loss of synchronization of the clock detecting a synchronization marker;

in response to the detection of the synchronization marker resynchronizing the clock; and

continuing reception of the plurality of frames of information after resynchronization of the clock.

238. A process in accordance with claim 237 wherein:

each of frames of information comprise an information field containing bits and error correction code containing bits; and

the detecting of loss of synchronization is produced by determining if at least one frame has at least one erroneous uncorrectable bit in the information field by processing the bits therein and the bits of the error correction code of the at least one frame.

239. A process in accordance with claim 237 wherein:

the synchronization marker is comprised of a plurality of bits which do not represent valid data.

240. A process in accordance with claim 238 wherein:

the synchronization marker is comprised of a plurality of bits which do not represent valid data.