Method and apparatus for storing vector data in multiple non-consecutive locations in a data processor using a mask value

• US 5,742,786 A
• Filed: 02/13/1995
• Issued: 04/21/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Lawell, Terry G., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US08/389,512
• Time in Patent Office: 1,163 Days
• Field of Search: 395/421.07, 395/800, 364/232.21, 364/259.7
• US Class Current: 711/217
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Claims

1. A data processor, comprising:

input means for receiving a first digital data value;

a memory storage circuit having a plurality of memory storage locations, each of the plurality of memory storage locations having a corresponding address and selectively storing one of a plurality of digital data values, a first memory storage location having a first address and storing the first digital data value, the memory storage circuit being coupled to the input means for receiving the first digital data value;

a pointer register for storing a first pointer value which corresponds to the first address, the pointer register being coupled to the memory storage circuit;

a mask register for storing a mask value, the mask value indicating a number of memory storage locations which receive and store the first digital data value, the mask register being coupled to the memory storage circuit; and

an increment circuit for incrementing the first pointer value by an increment value to provide an incremented pointer value, the incremented pointer value corresponding to a second address, the increment circuit being coupled to the pointer register for receiving the first pointer value;

wherein the increment value is generated using the mask value and wherein the first digital data value is stored in a second memory storage location corresponding to the second address when the mask value indicates that the number of memory storage locations which receive and store the first digital data value is greater than one, and wherein the first and second memory storage locations which store the first digital data value are non-consecutive if the increment value is greater than one.

2. The data processor of claim 1 wherein the mask value indicates a plurality of addresses wherein each of the plurality of addresses corresponds to one of the number of memory storage locations which receive and store the first digital data value.

3. The data processor of claim 2 wherein the mask value is represented by a plurality of mask bits, the plurality of masked bits being used to selectively determine each of the plurality of addresses which correspond to one of the number of memory storage locations which receive and store the first digital data value.

4. The data processor of claim 1 further comprising:

address generation circuitry for receiving the mask value and for generating the first and second addresses where the first and second addresses are non-consecutive, wherein a bit of the mask value having a predetermined binary value causes a corresponding address bit of the first address to have a binary one value while the corresponding address bit of the second address has a binary zero value.

5. The data processor of claim 1 wherein the increment value equals 2^X, where X is determined by the mask value and where X may be greater than 0.

6. The data processor of claim 1 wherein the pointer register is user programmable.

7. The data processor of claim 1 wherein the first digital data value is a first one of a plurality of digital data values.

8. The data processor of claim 7 further comprising:

a count register for storing a count value, the count value indicating a number of memory storage locations which receive and store the plurality of digital data values, each of the number of memory storage locations storing one of the plurality of digital data values, the count register being coupled to the memory storage circuit.

9. The data processor of claim 8 further comprising:

a decrement circuit for decrementing the count value by a decrement value to provide a decremented count value.

10. The data processor of claim 9 wherein the decrement value is dependent upon the mask value.

11. The data processor of claim 7 further comprising:

a timing storage circuit for storing a plurality of timing values wherein each one of the plurality of timing values corresponds to one of a plurality of ascending points in time, an external data source providing one of the plurality of digital data values to the input means at one of the ascending points in time, the timing storage circuit being coupled to the input means.

12. The data processor of claim 11 wherein each of the plurality of timing values indicates a point in time at which an external data source provides one of the plurality of digital data values to the input means.

13. The data processor of claim 7 further comprising:

an input timing register, the input timing register storing a first timing value which indicates a first point in time at which an external data source provides the first digital data value to the input means, the input timing register being coupled to the input means.

14. The data processor of claim 13 wherein the external data source provides a next one of the plurality of digital data values to the input means, the next one of the plurality of digital data values being provided at a second point in time which is consecutive with respect to the first point in time.

15. The data processor of claim 1 further comprising a control storage circuit for storing a control value for selecting one of a plurality of modes for storing data in the memory storage circuit, the control storage circuit being coupled to the memory storage circuit.

16. A method for storing digital data in a data processor, comprising the steps of:

receiving a first digital data value;

accessing a pointer value from a pointer register, a first pointer value corresponding to a first address of a first memory storage location in a memory storage circuit;

accessing a mask value from a mask register, the mask value indicating a number of memory storage locations in the memory storage circuit;

storing the first digital data value in the first memory storage location in the memory storage circuit; and

storing the first digital data value in a first plurality of non-consecutive memory storage locations in the memory storage circuit, the first plurality of non-consecutive memory storage locations corresponding to the number of memory storage locations indicated by the mask value.

17. The method of claim 16 wherein the step of storing the first digital data value in the memory storage circuit further comprises the steps of:

i) storing the pointer value in a shadow register as a shadow pointer value;

ii) storing the first digital data value in one of the plurality of memory storage locations indicated by the shadow pointer value;

iii) incrementing the shadow pointer value to provide an incremented shadow pointer value, the incremented shadow pointer value pointing to a next one of the plurality of memory storage locations in the memory storage circuit;

iv) storing the incremented shadow pointer value in the shadow register as the shadow pointer value; and

v) repeating steps ii) through iv) to access each of the number of memory storage locations indicated by the mask value.

18. The method of claim 17 further comprising the steps of:

receiving a second digital data value;

accessing the shadow pointer value from the shadow register, the shadow pointer value indicating a next consecutive one of the plurality of memory storage locations in the memory storage circuit;

accessing the mask value from the mask register;

storing the second digital data value in the next consecutive one of the plurality of memory storage locations;

incrementing the shadow pointer value;

storing the second digital data value in the one of the plurality of memory storage locations indicated by the shadow pointer value; and

storing the second digital data value in a second portion of the plurality of memory storage locations in the memory storage circuit, the second plurality memory storage locations corresponding to the number of memory storage locations indicated by the mask value.

19. The method of claim 16 further comprising the step of:

receiving a plurality of digital data values, a first one of the plurality of digital data values being the first digital data value.

20. The method of claim 19 further comprising the steps of:

accessing a count value from a count register, the count value indicating a number of memory storage locations which receive and store the plurality of digital data values; and

receiving the plurality of digital data values corresponding to the count value.

21. The method of claim 19 further comprising the step of:

accessing a first one of a plurality of timing values from a timing storage circuit, the first one of the plurality of timing values corresponding to a first one of a plurality of ascending points in time; and

receiving the first digital data value from an external integrated circuit at the first one of the plurality of ascending points in time.

22. The method of claim 21 further comprising the steps of:

accessing a second one of the plurality of timing values from the timing storage circuit, the second timing value corresponding to a second one of the plurality of ascending points in time; and

receiving a second one of the plurality of digital data values from the external integrated circuit at the second one of the plurality of ascending points in time.

23. The method of claim 19 further comprising the step of:

accessing a first timing value from an input timing register, the first timing value corresponding to a first point in time; and

receiving the first one of the plurality of digital data values from an external integrated circuit at the first point in time.

24. The method of claim 23 further comprising the steps of:

receiving a second one of the plurality of digital data values at a second point in time, the second point in time being consecutive to the first point in time.