Hardware reset of a write state machine for flash memory
First Claim
1. A method of aborting an automated write sequence in a memory device, the method comprising the steps of:
- (A) commencing the write sequence upon receipt of a command, wherein the write sequence includes a plurality of operations being performed by a write state machine on a nonvolatile memory array of the memory device;
(B) detecting an abort signal during each operation of the write sequence, the abort signal capable of being in one of a first and second state;
(C) halting the write sequence by ramping down a write voltage supplied to the nonvolatile memory array if the write state machine detects the abort signal in the first state, and continuing with the write sequence if the write state machine detects the abort signal in the second state; and
(D) placing the nonvolatile memory array in a read-only mode if the abort signal is in the first state.
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Accused Products
Abstract
A method of quickly aborting an automated program or erase sequence on a nonvolatile memory array in which each operation of the sequence is performed by a write state machine. During each operation of the program or erase sequence, the state of an abort signal is detected to determine whether or not the sequence should be aborted. If the abort signal is in a second state, the sequence continues to the next operation. If the abort signal is in a first state, the write state machine aborts the sequence and the nonvolatile memory array is placed in a read-only mode. The nonvolatile memory array is then available for user access.
82 Citations
17 Claims
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1. A method of aborting an automated write sequence in a memory device, the method comprising the steps of:
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(A) commencing the write sequence upon receipt of a command, wherein the write sequence includes a plurality of operations being performed by a write state machine on a nonvolatile memory array of the memory device; (B) detecting an abort signal during each operation of the write sequence, the abort signal capable of being in one of a first and second state; (C) halting the write sequence by ramping down a write voltage supplied to the nonvolatile memory array if the write state machine detects the abort signal in the first state, and continuing with the write sequence if the write state machine detects the abort signal in the second state; and (D) placing the nonvolatile memory array in a read-only mode if the abort signal is in the first state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of aborting an automated write sequence in a memory device, the memory device including a write state machine, voltage control circuitry, and a nonvolatile memory array, the method comprising the steps of:
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(A) initiating the write sequence, wherein the write sequence is performed by the write state machine on the nonvolatile memory array of the memory device; (B) aborting the write sequence once the write sequence has commenced, wherein the write state machine halts the write sequence and the voltage control circuitry places the nonvolatile memory array in a read-only mode by ramping down a write voltage supplied to the nonvolatile memory array; and (C) subsequently reading data from the nonvolatile memory array. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A flash memory device, comprising:
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(A) a flash memory array capable of being erased and programmed; (B) a voltage control circuit for placing the flash memory array in a read-only mode; (C) a write state machine, coupled to the voltage control circuit, for automatically performing a write sequence on the flash memory array upon receipt of a command, wherein the write sequence includes a plurality of operations; and (D) an abort signal, coupled to the write state machine, such that each operation of the write sequence is performed if the abort signal is in a second state, and the write sequence is aborted if the abort signal is in a first state, wherein when the write sequence is aborted the voltage control circuitry puts the flash memory array into the read-only mode by ramping down a write voltage supplied to the flash memory array. - View Dependent Claims (14, 15, 16)
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17. memory device, comprising:
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(A) means for automatically performing a write sequence upon receipt of a command, wherein the write sequence includes a plurality of operations being performed on a nonvolatile memory array; (B) means for detecting an abort signal during each operation of the write sequence, the abort signal capable of being in one of a first and second state; (C) means for halting the write sequence by ramping down a write voltage supplied to the nonvolatile memory array if the abort signal is detected in the first state, and continuing with the write sequence if the abort signal is detected in the second state; and (D) means for placing the nonvolatile memory array in a read-only mode if abort signal is detected in the first state.
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Specification