Method and apparatus for providing a configurable display memory for single buffered and double buffered application programs to be run singly or simultaneously

• US 5,742,788 A
• Filed: 06/27/1994
• Issued: 04/21/1998
• Est. Priority Date: 07/26/1991
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Moffat, Guy, McIntyre, Bruce, Priem, Curtis, Malachowsky, Chris
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US08/266,095
• Time in Patent Office: 1,394 Days
• Field of Search: 395/428, 395/484, 395/495
• US Class Current: 711/110
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Claims

1. A method for arranging a video random access memory array to provide a plurality of frame buffers for an output display by which single buffered and double buffered applications may be run singly or simultaneously, said method comprising the steps of:

configuring said memory array to form a plurality of frame buffers depending upon which applications are running, said configuring step comprising the steps of;

configuring said memory array to form a single frame buffer if only single buffer applications are running;

configuring said memory array to form a first visible frame buffer and a second visible frame buffer if one double buffered application is running;

configuring said memory array to form a receive frame buffer to receive data and a transmit frame buffer to transmit data if a plurality of double buffered applications are running;

writing data to said memory array depending upon whether said applications are single or double buffered, said writing data step comprising the steps of;

writing to said single frame buffer if only single buffer applications are running;

simultaneously writing single buffered application data to both of said frame buffers when double buffered applications are running;

selecting data to be furnished to said output display from said frame buffers, said selecting data step comprising the steps of;

selecting data from said single frame buffer when only single buffer applications are running;

selecting data from the frame buffer, of said first and second visible frame buffers, to which no data is being written when one double buffered application is running;

selecting data from said transmit frame buffer when a plurality of double buffered applications are running.

2. The method as set forth in claim 1, wherein when said memory array is configured to form a first visible frame buffer and a second visible frame buffer then said writing step further comprises the step of:

writing data from said double buffered application to a frame buffer to which no data is being selected from.

3. The method as set forth in claim 1, wherein when said memory array is configured to form a receive frame buffer to receive data and a transmit frame buffer to transmit data then said writing data step further comprises the steps of:

writing data from said double buffered applications to said receive frame buffer;

copying data from said receive frame buffer to said transmit frame buffer by simultaneously selecting the same row and column addresses for both of said frame buffers, wherein data is read from said receive frame buffer and said data is written to said transmit frame buffer during the same operation.

4. A computer system that generates signals for displaying data, said computer system comprising:

a microprocessor;

an output display;

an array of video random access memory sufficient for storing at least two complete frames of output display data;

means for determining whether a program running on said microprocessor is designed to run in a single buffer environment or a double buffer environment;

means for tracking the number of programs running on said microprocessor designed to be run in a double buffered environment;

means for configuring said memory array to form a single frame buffer when used with programs designed to run in a single buffer environment, said means of configuring controlled by said means for determining and said means for tracking; and

means for selecting data to be furnished to said output display, said means for selecting controlled by said means for tracking.

5. The computer system as set forth in claim 4, wherein said means for configuring said memory array forms:

a single frame buffer when used with programs designed to run in a single buffer environment;

a first visible frame buffer and a second visible frame buffer when used with one program designed to run in a double buffer environment; and

a receive frame buffer to receive data and a transmit frame buffer to transmit data when used with a plurality of programs designed to run in a double buffered environment.

6. The computer system as set forth in claim 4, wherein:

said means for selecting data to be furnished depends on whether said program running is designed to be run in a single buffer environment, or a double buffer environment.

7. The computer system as set forth in claim 5, wherein said means for configuring comprises:

control means for responding to a plurality of programs designed to run in a double buffer environment, said control means configuring said memory array to form a receive frame buffer to receive display data, and a transmit frame buffer for transferring said display data to said output display, wherein fast copying data from said first frame buffer to said second frame buffer is used.

8. The computer system as set forth in claim 7, wherein said control means comprises:

means for writing said display data only to said receive frame buffer;

means for simultaneously selecting identical addresses for said receive frame buffer and said transmit frame buffer; and

means for reading said display data from the receive frame buffer and writing said display data to said transmit frame buffer simultaneously.

9. The computer system as set forth in claim 6, wherein:

said means for selecting causes all data associated with programs designed to be run in a single buffer environment to be written to both frame buffers simultaneously when said means for configuring causes two frame buffers to be formed.

10. The computer system as set forth in claim 9, wherein said means for selecting further comprises:

means for selecting data from different portions of said array; and

means for transferring said selected data from a portion of said array, wherein said array is configured as one pair of frame buffers when only one double buffered program is running.

11. The computer system as set forth in claim 10, wherein the means for transferring comprises:

a multiplexer;

means for storing a first signal indicating that said multiplexer is to select a different frame buffer for furnishing data to an output display; and

means for furnishing said first signal to said multiplexer only when a frame on said output display is completely scanned and before a new frame commences.

12. The computer system as set forth in claim 11, wherein said means for furnishing comprises:

means for deriving a second signal from a video timing generator or control circuitry, indicating when the raster scan reaches the bottom of said output display and vertical retrace begins; and

means for using said second signal from said video timing generator or control circuitry to furnish said first signal to said multiplexer means.