Fabrication of complementary field-effect transistors each having multi-part channel

• US 5,744,372 A
• Filed: 06/01/1995
• Issued: 04/28/1998
• Est. Priority Date: 04/12/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bulucea, Constantin
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/456,454
• Time in Patent Office: 1,062 Days
• Field of Search: 437/40 DM, 437/41 DM, 437/40 AS, 437/41 AS, 437/44, 437/34, 437/56, 437/57, 257/336, 257/338, 257/369, 257/372, 257/373
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating the complementary transistor structure, the threshold body zone of each transistor is formed at the same time as the drain extension of the other transistor.

Claims

1. A method of fabricating a complementary transistor structure from a semiconductive body having a device region of a first conductivity type and a device region of a second conductivity type opposite to the first conductivity type, the structure including (a) first source and drain zones of the second conductivity type laterally separated by a first channel zone in the first device region, the first drain zone comprising a first main drain portion and a more lightly doped first drain extension located between the first channel zone and the first main drain portion, the first channel zone comprising a first output channel portion and a more heavily doped first input channel portion that respectively meet the first drain extension and the first source zone, and (b) second source and drain zones of the first conductivity type laterally separated by a second channel zone in the second device region, the second drain zone comprising a second main drain portion and a more lightly doped second drain extension located between the second channel zone and the second main drain portion, the second channel zone comprising a second output channel portion and a more heavily doped second input channel portion that respectively meet the second drain extension and the second source zone, the method comprising the steps of:

providing first and second gate electrodes respectively above, and insulatingly spaced apart from, the first and second device regions;

introducing first semiconductor dopant of the first conductivity type simultaneously (a) into part of the first channel zone to define the first input channel portion and (b) into part of the second device region to define the second drain extension;

introducing second semiconductor dopant of the second conductivity type simultaneously (a) into part of the second channel zone to define the second input channel portion and (b) into part of the first device region to define the first drain extension; and

introducing (a) third semiconductor dopant of the second conductivity type into a pair of laterally separated parts of the first device region to define the first source zone and the first main drain portion continuous with the first drain extension and (b) fourth semiconductor dopant of the first conductivity type into a pair of laterally separated parts of the second device region to define the second source zone and the second main drain portion continuous with the second drain extension.

2. A method as in claim 1 wherein the first and second drain extensions substantially extend at least as deep into the semiconductive body respectively as the first and second main drain portions.

3. A method as in claim 2 wherein:

the first gate electrode comprises non-monocrystalline semiconductive material of the second conductivity type; and

the second gate electrode comprises non-monocrystalline semiconductive material of the first conductivity type.

4. A method as in claim 2 wherein the first and second introducing steps are initiated before the third introducing step.

5. A method as in claim 2 wherein:

the first and second introducing steps comprise ion implanting the first and second dopants into the semiconductive body and then thermally driving the first and second dopants further into the semiconductive body;

the gate electrodes and any electrically insulating material along their sides serve as a shield during the ion implantation of the first and second dopants so as to largely prevent the first and second dopants from directly entering underlying material of the semiconductive body;

a first mask is provided over intended locations for the second input channel portion and the first drain extension during the ion implantation of the first dopant so as to largely prevent the first dopant from directly entering the locations for the second input channel portion and the first drain extension; and

a second mask is provided over intended locations for the first input channel portion and second drain extension during the ion implantation of the second dopant so as to largely prevent the second dopant from directly entering the locations for the first input channel portion and the second drain extension.

6. A method as in claim 5 further including, subsequent to the first and second introducing steps but prior to the third introducing step, the step of providing spacers alongside the gate electrodes to a greater thickness than any electrically insulating material alongside the spacers during the ion implantation of the first and second dopants, wherein:

the third introducing step comprises ion implanting the third and fourth dopants into the semiconductive body and then thermally driving the third and fourth dopants further into the semiconductive body; and

the gate electrodes and the spacers serve as a shield during the ion implantation of the third and fourth dopants to largely prevent the third and fourth dopants from directly entering underlying material of the semiconductive body.

7. A method as in claim 1 wherein:

the first input channel portion is part of a first source-adjoining threshold body zone of the first conductivity type substantially extending at least as deep into the semiconductive body as the first source zone;

the second input channel portion is part of a second source-adjoining threshold body zone of the second conductivity type substantially extending at least as deep into the semiconductive body as the second source zone; and

each of the threshold body zones and the drain extensions reaches a maximum net dopant concentration at a depth of no more than 0.05 μ

m into the semiconductive body.

8. A method as in claim 1 wherein:

the first input channel portion is part of a first source-adjoining threshold body zone of the first conductivity type substantially extending at least as deep into the semiconductive body as the first source zone;

the second input channel portion is part of a second source-adjoining threshold body zone of the second conductivity type substantially extending at least as deep into the semiconductive body as the second source zone; and

each of the threshold body zones and the drain extensions reaches a maximum net dopant concentration at a depth of at least 0.05 μ

m into the semiconductive body.

9. A method as in claim 1 wherein the second and third introducing steps are performed such that the first gate electrode extends partially over both the first drain extension and the first main drain portion.

10. A method as in claim 9 wherein the first and third introducing steps are performed such that the second gate electrode extends partially over both the second drain extension and the second main drain portion.

11. A method as in claim 9 wherein the second introducing step comprises ion implanting the second dopant using the first gate electrode as an implant shield.

12. A method of as in claim 9 wherein the second introducing step is performed in such a manner that the first drain extension reaches a maximum lateral distance under the first gate electrode at a location spaced downwardly apart from the first gate electrode.