Silicon carbide semiconductor device and process for its production

• US 5,744,826 A
• Filed: 01/22/1997
• Issued: 04/28/1998
• Est. Priority Date: 01/23/1996
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Takeuchi, Yuichi, Tokura, Norihito, Miyajima, Takeshi, Fuma, Hiroo, Murata, Toshio
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Wille, Douglas A.
• Application Number:
  US08/785,952
• Time in Patent Office: 461 Days
• Field of Search: 257/77, 257/328, 257/330, 438/931
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A semiconductor substrate 4 consisting of an n⁺ -type substrate 1, an n^- -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3, made of hexagonal crystal-based single crystal silicon carbide with the main surface having a planar orientation approximately in the (0001) carbon face. An n⁺ -type source region 5 is formed in the surface layer of the semiconductor layer 3, and a trench 7 runs from the main surface through the region 5 and the semiconductor layer 3 reaching to the semiconductor layer 2, and extending approximately in the 1120! direction. An n-type silicon carbide semiconductor thin-film layer 8 is provided on the region 5, the semiconductor layer 3 and the semiconductor layer 2 on the side walls of the trench 7, while a gate electrode layer 10 is formed on the inner side of a gate insulating film 9, a source electrode layer 12 is formed on the surface of the semiconductor region 5, and a drain electrode layer 13 is formed on the surface of the n⁺ -type substrate 1.

Claims

1. A silicon carbide semiconductor device, comprising:

a single crystal hexagonal silicon carbide semiconductor substrate comprising a stack of a first semiconductor layer of a first conductivity-type, a second semiconductor layer of the first conductivity-type having an electric resistance higher than that of said first semiconductor layer, and a third semiconductor layer of a second conductivity-type in this order, said third semiconductor layer having a main surface of a carbon face with a face orientation of about (0001);

a semiconductor region of the first conductivity-type formed in a predetermined region of said third semiconductor layer in a layer adjacent to said main surface of said third semiconductor layer;

a trench extending from said main surface through said semiconductor region and said third semiconductor layer and reaching said second semiconductor layer, said trench having side walls extending in the direction of 1120!;

a fourth semiconductor layer of silicon carbide extending on said side walls of said semiconductor region, said third semiconductor layer and said second semiconductor layer in said trench, said fourth semiconductor layer having a surface;

a gate insulating film formed at least on said surface of said fourth semiconductor layer;

a gate electrode layer formed inside said gate insulating film in said trench;

a first electrode layer formed on at least a portion of said semiconductor region; and

a second electrode layer formed on a surface of said first semiconductor layer.

2. The silicon carbide semiconductor device according to claim 1, wherein said trench has a planar shape of a hexagon with almost equal inner angles formed by said side walls thereof.

3. The silicon carbide semiconductor device according to claim 1, wherein said fourth semiconductor layer has an impurity concentration lower than those of said first and third semiconductor layers.

4. A process for manufacturing a silicon carbide semiconductor device, comprising the steps of:

epitaxially growing, on a first semiconductor layer of hexagonal single crystal silicon carbide of a first conductivity-type, a second semiconductor layer of the first conductivity-type having an electric resistance higher than that of said first semiconductor layer, and a third semiconductor layer of a second conductivity-type in this order, to form a hexagonal single crystal silicon carbide semiconductor substrate comprising the first to third semiconductor layers, said third semiconductor layer having a main surface of a carbon face with a face orientation of about (0001);

forming a semiconductor region of the first conductivity-type in a predetermined region of said third semiconductor layer in a layer adjacent to said main surface of said third semiconductor layer;

forming a trench extending from said main surface through said semiconductor region and said third semiconductor layer and reaching said second semiconductor layer, said trench having side walls extending in the direction of 1120!;

growing a fourth semiconductor layer of silicon carbide entirely including on an inner surface of said trench, said fourth semiconductor layer having a thickness thicker on said side walls of said trench than in other regions;

thermally oxidizing said fourth semiconductor layer so as to completely oxidize said fourth semiconductor layer other than a region on said side walls of said trench, the oxidized semiconductor layer having a thickness thicker on the bottom of said trench than on said side walls thereof, to thereby selectively leave said fourth semiconductor layer on said side walls of said trench and form a gate insulating layer on said fourth semiconductor layer in said trench;

forming a gate electrode layer inside said gate insulating film in said trench;

forming a first electrode layer on at least a portion of said semiconductor region; and

forming a second electrode layer on a surface of said first semiconductor layer.