Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements

• US 5,744,827 A
• Filed: 11/26/1996
• Issued: 04/28/1998
• Est. Priority Date: 11/28/1995
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Hyeon Jo, Ahn, Seung Ho, Choi, Ki Won, Jeong, Do Soo, An, Min Cheol
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/753,532
• Time in Patent Office: 518 Days
• Field of Search: 257/686, 257/669, 257/672, 257/673, 257/674, 257/676, 257/685, 257/692, 257/693, 257/696, 257/698, 257/737, 257/738, 257/784, 257/666, 257/706, 257/723, 257/730, 257/731
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

Claims

1. A three dimensional stack package device comprising a plurality of individual semiconductor devices, each of said plurality of individual semiconductor devices comprising:

a semiconductor chip;

a protective body for encapsulating said semiconductor chip;

a lead frame comprising

inner lead portions which are electrically interconnected to the semiconductor chip and included within the protective body,

outer lead portions formed as a single body with the inner lead portions, and

coupling lead portions located between the inner and the outer lead portions and having a top surface exposed upward from the protective body; and

a plurality of vertical interconnection means attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions,

wherein, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnections means, and an electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

2. The three dimensional stack package device as claimed in claim 1, wherein the outer lead portions of the lowermost individual semiconductor device are protruding from the protective body and formed into a shape, and the outer lead portions of the remaining of the plurality of semiconductor devices are cut off and removed.

3. The three dimensional stack package device as claimed in claim 2, wherein the outer lead portions of the lowermost individual semiconductor device are formed into a J-shape so that the three dimensional device can be surface-mounted on a external circuit board.

4. The three dimensional stack package device as claimed in claim 2, wherein the outer lead portions of the lowermost individual semiconductor device are formed into a gull-wing shape so that the three dimensional device can be surface-mounted on a external circuit board.

5. The three dimensional stack package device as claimed in claim 2, wherein the outer lead portions of the lowermost individual semiconductor device are formed into a shape for the three dimensional device to be mounted on an external circuit board in a pin insertion manner.

6. The three dimensional stack package device as claimed in claim 1, wherein the outer lead portions of said plurality of individual semiconductor devices are all cut off and removed, wherein the exposed vertical interconnection means of the lowermost individual semiconductor device are attached with a first plurality of solder balls, and the electrical interconnection of the three dimensional stack package device is accomplished by said first plurality of solder balls.

7. The three dimensional stack package device as claimed in claim 2, wherein the coupling lead portions of a lower of said plurality of individual semiconductor devices, and the vertical interconnection means of an upper of said plurality of individual semiconductor devices, are coupled by way of a second plurality of solder balls, such that spaces are formed between the upper and the lower individual semiconductor devices so that heat from the individual semiconductor devices are dissipated through the spaces.

8. The three dimensional stack package device as claimed in claim 6, wherein the coupling lead portions of a lower of said plurality of individual semiconductor devices, and the vertical interconnection means of an upper of said plurality of individual semiconductor devices, are coupled by way of a second plurality of solder balls, such that spaces are formed between the upper and the lower individual semiconductor devices so that heat from the individual semiconductor devices are dissipated through the spaces.

9. The three dimensional stack package device as claimed in claim 1, wherein the vertical interconnection means have a shape of right-hexahedron.

10. The three dimensional stack package device as claimed in claim 1, wherein the vertical interconnection means are made of a same material as the lead frame.

11. The three dimensional stack package device as claimed in claim 1, wherein both the exposed coupling lead portions and the exposed vertical interconnection means are plated with a tin-lead alloy.

12. The three dimensional stack package device as claimed in claim 1, wherein the coupling lead portions and the vertical interconnection means are coupled by a thermal-compression method.

13. The three dimensional stack package device as claimed in claim 1, wherein the inner lead portions are attached to a top surface of the individual semiconductor device, and the inner lead portions are electrically interconnected to the individual semiconductor devices by way of bonding wires.

14. The three dimensional stack package device as claimed in claim 1, wherein the inner lead portions are electrically interconnected to the individual semiconductor devices by way of metal bumps.

15. The three dimensional stack package device as claimed in claim 1, wherein said plurality of individual semiconductor devices are memory devices, and first inner leads of each memory device, which are associated with address signals, controlling signals for selecting row addresses and column addresses and power supply signals, are arranged at same positions with respect to corresponding inner leads of its neighboring upper and lower memory devices, while second inner leads of each memory device, which are associated with input and output data, are arranged in different positions with respect to corresponding inner leads of its neighboring upper and lower memory devices.

16. The three dimensional stack package device as claimed in claim 1, wherein said plurality of individual semiconductor devices comprise power supply leads, ground leads and a capacitor connected between the power supply and ground leads.

17. The three dimensional stack package device as claimed in claim 1, wherein said plurality of individual semiconductor devices comprise power supply leads and ground leads, and a capacitor is connected between the exposed coupling lead portions corresponding to the power supply leads and ground leads.

18. The three dimensional stack package device as claimed in claim 1, wherein the exposed coupling lead portions of an uppermost individual semiconductor device is attached to probe pins for testing the three dimensional stack package device.

19. The three dimensional stack package device as claimed in claim 1, wherein said vertical interconnection means are attached to the coupling lead portions by a method comprising the steps of:

attaching a column of right-hexahedron shaped material to the back side of the coupling lead portions in a direction that the inner leads are arranged; and

cutting and removing portions of the column of right-hexahedron material between neighboring inner leads.

20. The three dimensional stack package device as claimed in claim 1, wherein the outer leads portions of said plurality of individual semiconductor devices are cut off and removed, a circuit board is, at its top surface, attached to a back side of the lowermost semiconductor device, said circuit board comprising a third plurality of solder balls bonded to a bottom surface thereof and conductive wiring patterns which are electrically interconnected both to the exposed coupling lead portions of the lowermost semiconductor device and to the third plurality of solder balls, so that the electrical interconnection of the three dimensional stack package device is accomplished by the third plurality of solder balls.

21. The three dimensional stack package device as claimed in claim 20, wherein said third plurality of solder balls are disposed in an array at the bottom surface of the circuit board.

22. The three dimensional stack package device as claimed in claim 2, wherein said exposed coupling lead portions and vertical interconnection means are protruding from the protective body so that air paths are formed between upper and lower of said plurality of individual semiconductor devices.

23. The three dimensional stack package device as claimed in claim 6, wherein said exposed coupling lead portions and vertical interconnection means are protruding from the protective body so that air paths are formed between upper and lower of said plurality of individual semiconductor devices.

24. The three dimensional stack package device as claimed in claim 2, wherein the electrical interconnection of the coupling lead portions and the vertical interconnection means are accomplished by a method comprising the steps of:

depositing solder creams on the exposed coupling lead portions;

aligning the coupling lead portions with the vertical interconnection means; and

heating the coupling lead portions and the vertical interconnection means to about 180°

C.

25. The three dimensional stack package device as claimed in claim 6, wherein the electrical interconnection of the coupling lead portions and the vertical interconnection means are accomplished by a method comprising the steps of:

depositing solder creams on the exposed coupling lead portions;

aligning the coupling lead portions with the vertical interconnection means; and

heating the coupling lead portions and the vertical interconnection means to about 180°

C.

26. The three dimensional stack package device as claimed in claim 7, wherein the coupling lead portions and the vertical interconnection means are accomplished by a method comprising the steps of:

plating solder resists on the back side of the individual semiconductor device expect for the exposed vertical interconnection means;

aligning the coupling lead portions, vertical interconnection means and the second plurality of solder balls; and

heating the coupling lead portions, vertical interconnection means and the second plurality of solder balls.

27. The three dimensional stack package device as claimed in claim 8, wherein the coupling of the coupling lead portions and the vertical interconnection means are accomplished by a method comprising the steps of:

plating solder resists on the back side of the individual semiconductor device expect for the exposed vertical interconnection means;

aligning the coupling lead portions, vertical interconnection means and the second plurality of solder balls; and

heating the coupling lead portions, vertical interconnection means and the second plurality of solder balls.

28. The three dimensional stack package device as claimed in claim 1, wherein the vertical interconnection means are metal balls.