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CMOS SRAM cell

  • US 5,744,844 A
  • Filed: 11/19/1996
  • Issued: 04/28/1998
  • Est. Priority Date: 03/29/1996
  • Status: Expired due to Term
First Claim
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1. A semiconductor device having an SRAM cell therein, said SRAM cell comprising:

  • a first nMOS region of a semiconductor substrate, said first nMOS region including first and third nMOS transistors therein;

    a second nMOS region of the semiconductor substrate having second and fourth nMOS transistors therein;

    a pMOS region disposed between said first and second nMOS regions, said pMOS region having first and second pMOS transistors therein, said first to fourth nMOS transistors and said first and second pMOS transistors being formed on the semiconductor substrate;

    isolation regions between said first nMOS region and said pMOS region and between said second nMOS region and said pMOS region;

    first and second bit lines extending in a direction substantially perpendicular to a longitudinal region extending from said first nMOS region to said second nMOS region;

    said SRAM cell further comprisinga word line extending in a direction parallel to said longitudinal region,wherein said first and second nMOS transistors and said first and second pMOS transistors comprise a flip-flop for storing data, wherein said third nMOS transistor forms a first transfer gate connected between the first bit line and the flip-flop, with a gate thereof connected with said word line, and wherein said fourth nMOS transistor forms a second transfer gate connected between said second bit line and said flip-flop with a gate thereof connected with said word line.

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