CMOS SRAM cell

• US 5,744,844 A
• Filed: 11/19/1996
• Issued: 04/28/1998
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Higuchi, Tsuyoshi
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US08/752,631
• Time in Patent Office: 525 Days
• Field of Search: 257/208, 257/211, 257/369, 257/903, 257/368, 257/370, 257/904, 365/189.11
• US Class Current: 257/369
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

An outline of an SRAM cell is rectangular. The SRAM cell have nMOS transistors QN1 and QN3 in a nMOS region 13A being on one side of the longitudinal direction, nMOS transistors QN2 and QN4 in a nMOS region 13B being on the opposite side thereof, pMOS transistors QP1 and QP2 in a central region 12, and isolation regions 14A and 14B being between the regions 13A and 12 and between the regions 13B and 12 respectively. The pMOS transistors QP1 and QP2 are on the nMOS transistor QN1 side and on the nMOS transistor QN2 side respectively within the region 12. The direction of bit lines is perpendicular to the longitudinal direction and the word line is parallel to the longitudinal direction. The nMOS transistors QN1, QN4 and the pMOS transistor QP1 are placed on one side of the regions 13A, 13B and 12 respectively in the direction perpendicular to the longitudinal direction, whereas the nMOS transistors QN3 and QN2 and the pMOS transistor QP2 are placed on the opposite side thereof.

Claims

1. A semiconductor device having an SRAM cell therein, said SRAM cell comprising:

a first nMOS region of a semiconductor substrate, said first nMOS region including first and third nMOS transistors therein;

a second nMOS region of the semiconductor substrate having second and fourth nMOS transistors therein;

a pMOS region disposed between said first and second nMOS regions, said pMOS region having first and second pMOS transistors therein, said first to fourth nMOS transistors and said first and second pMOS transistors being formed on the semiconductor substrate;

isolation regions between said first nMOS region and said pMOS region and between said second nMOS region and said pMOS region;

first and second bit lines extending in a direction substantially perpendicular to a longitudinal region extending from said first nMOS region to said second nMOS region;

said SRAM cell further comprising

a word line extending in a direction parallel to said longitudinal region,

wherein said first and second nMOS transistors and said first and second pMOS transistors comprise a flip-flop for storing data, wherein said third nMOS transistor forms a first transfer gate connected between the first bit line and the flip-flop, with a gate thereof connected with said word line, and wherein said fourth nMOS transistor forms a second transfer gate connected between said second bit line and said flip-flop with a gate thereof connected with said word line.

2. A semiconductor device according to claim 1, wherein said first pMOS transistor and said first nMOS transistor are connected in series with each other between a source potential supply line and a reference potential supply line, with a gate of said first pMOS transistor and a gate of said first nMOS transistor short-circuited to each other,

wherein said second pMOS transistor and said second nMOS transistor are connected in series with each other between said source potential supply line and said reference potential supply line, with a gate of said second pMOS transistor and a gate of said second nMOS transistor short-circuited to each other,

wherein said third nMOS transistor is connected between said first bit line and a drain of said first nMOS transistor,

wherein said fourth nMOS transistor is connected between the second bit line and a drain of said second nMOS transistor, and wherein the gate of said first pMOS transistor is connected to the drain of said second nMOS transistor and the gate of said second pMOS transistor is connected to the drain of said first nMOS transistor.

3. A semiconductor device according to claim 1, wherein said first and fourth nMOS transistors and said first pMOS transistor are each provided at a first side of said first and second nMOS regions and said pMOS region in a direction substantially perpendicular to said longitudinal region, and wherein said third and second nMOS transistors and said second pMOS transistors are each provided at a second side of said first and second regions and said pMOS region in a direction which is substantially perpendicular to said longitudinal region.

4. A semiconductor device according to claim 3, wherein said first and third nMOS transistors are arranged on the semiconductor substrate in a direction substantially perpendicular to said longitudinal region, and wherein said first and third nMOS transistors have a common n-type semiconductor area on the semiconductor substrate, and wherein said second and fourth nMOS transistors are arranged on the semiconductor substrate in a direction substantially perpendicular to said longitudinal region, and wherein said second and fourth nMOS transistors have a common n-type semiconductor area.

5. A semiconductor device according to claim 4, wherein said first pMOS transistor is disposed in an area of said pMOS region which is adjacent said first nMOS region, and wherein said second pMOS transistor is disposed in an area of said pMOS region which is adjacent said second nMOS region.

6. A semiconductor device according to claim 5, wherein a gate of said first nMOS transistor and a gate of said first pMOS transistor comprise first polysilicon wiring, said first polysilicon wiring being connected through a contact hole to the drain of said second pMOS transistor, and wherein a gate of said second nMOS transistor and a gate of said second pMOS transistor comprise second polysilicon wiring, said second polysilicon wiring being connected through a contact hole to the drain of said first pMOS transistor.

7. A semiconductor device according to claim 2, wherein an outer periphery of said SRAM cell has a rectangular shape.

8. A semiconductor device according to claim 7, wherein said source potential supply line is disposed in an area of said semiconductor substrate over said pMOS region, along a direction which is approximately perpendicular to said longitudinal region, and wherein said reference potential supply line is disposed along a side of said SRAM cell, in a direction which is substantially perpendicular to said longitudinal region, wherein said reference potential supply line and said source potential supply line define opposing sides of said rectangular shaped outer periphery.

9. A semiconductor device according to claim 8, wherein a pattern layout of the SRAM cell is symmetrical with respect to a center thereof.

10. A semiconductor device, comprising:

a memory cell array; and

a peripheral circuit connected to said memory cell array for performing data write and read operations for said memory cell array,

wherein said memory cell array comprises a plurality of CMOS SRAM cells disposed in a lattice configuration, each of said plurality of CMOS SRAM cells comprising

a first nMOS region including first and third nMOS transistors therein;

a second nMOS region having second and fourth nMOS transistors therein;

a pMOS region disposed between said first and second nMOS regions, said pMOS region having first and second pMOS transistors therein;

isolation regions between said first nMOS region and said pMOS region and between said second nMOS region and said pMOS region;

first and second bit lines extending in a direction substantially perpendicular to a longitudinal region extending from said first nMOS region to said second nMOS region;

said CMOS SRAM cell further comprising

a word line extending in a direction parallel to said longitudinal region,

wherein said first and second nMOS transistors and said first and second pMOS transistors comprise a flip-flop for storing data, wherein said third nMOS transistor forms a first transfer gate connected between the first bit line and the flip-flop, with a gate thereof connected with said word line, and wherein said fourth nMOS transistor forms a second transfer gate connected between said second bit line and said flip-flop with a gate thereof connected with said word line.

11. A semiconductor device according to claim 10, wherein each CMOS SRAM cell has a pattern layout with an outer periphery in a rectangular shape, said pattern layout being symmetrical with respect to a center thereof.

12. A semiconductor device according to claim 11, wherein said plurality of CMOS SRAM cells comprise a first-type CMOS SRAM cell and a second-type CMOS SRAM cell, said first type and said second type cells having corresponding outer peripheries,

wherein said first-type and said second-type CMOS SRAM cells are alternately arranged in blocks in a direction parallel to said bit lines and wherein outer peripheries of the first-type and said second-type CMOS SRAM cells are substantially symmetrical with respect to a boundary line between said first-type and said second-type CMOS SRAM cells which are adjacent each other.

13. A semiconductor device according to claim 12, wherein a gate of said third nMOS transistor of said first-type CMOS SRAM cell is connected to the word line corresponding to the first-type CMOS SRAM cell, wherein a gate of said fourth nMOS transistor of said second-type CMOS SRAM cell is connected by gate wiring to the gate of said third nMOS transistor of an adjacent first-type CMOS SRAM cell, wherein a gate of said fourth nMOS transistor of said first-type CMOS SRAM cell is connected to the corresponding word line, and wherein a gate of the third nMOS transistor of the second-type CMOS SRAM cell is connected by gate wiring to the gate of said fourth nMOS transistor of the adjacent first-type CMOS SRAM cell.

14. A semiconductor device according to claim 13, further comprising first and second data lines arranged parallel to said first and second bit lines for each of said CMOS SRAM cells, wherein said first and second data lines are connected to said first and second bit lines, respectively, and wherein said first and second bit lines are automatically located when said each CMOS SRAM cell is arranged, and wherein the first and second data lines are connected to data bus lines which are located between the CMOS SRAM cell blocks.