Semiconductor device

• US 5,744,857 A
• Filed: 08/09/1996
• Issued: 04/28/1998
• Est. Priority Date: 01/30/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamamoto, Yousuke
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/694,625
• Time in Patent Office: 627 Days
• Field of Search: 257/622, 257/624, 257/81, 257/98, 257/99, 257/625, 257/621
• US Class Current: 257/622
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A semiconductor device includes a silicon substrate having a surface and a 20˜150 μm deep recess produced at the surface by anisotropic etching, the recess having a bottom and a plurality of side walls; an electrode disposed on a region at the bottom of the recess, the region including an element region where a semiconductor element is to be mounted and a wire bonding region where a wire is to be bonded; a semiconductor element mounted on a portion of the electrode within the element region; and a wire bonded to a portion of the electrode within the wire bonding region. In this semiconductor device, since the electrode is disposed at the flat bottom of the recess, there is no difference in level, i.e., no step, in the region, where the electrode is disposed, between the element region and the wire bonding region. Therefore, unwanted breaking of the electrode is avoided, and degradation of characteristics due to such a breaking is avoided.

Claims

1. A semiconductor device comprising:

a silicon substrate having a surface and a recess 20˜

150 μ

m deep at the surface, the recess having a bottom and a plurality of side walls;

an electrode disposed on a region at the bottom of the recess, the region including an element region where a semiconductor element is mounted and a wire bonding region where a wire is bonded;

a semiconductor element mounted on a portion of the electrode within the element region; and

a wire bonded to a portion of the electrode within the wire bonding region.

2. The semiconductor device of claim 1 wherein the substrate has a convex region 5˜

20 μ

m high in the recess, and the electrode is disposed on the convex portion.

3. The semiconductor device of claim 1 wherein:

the substrate has a convex region 5˜

20 μ

m high in the recess;

the electrode is disposed on the bottom of the recess including the convex portion;

the semiconductor element is mounted on a portion of the electrode on the convex portion; and

the wire is bonded to a portion of the electrode outside the convex portion.

4. The semiconductor device of claim 1 wherein:

the surface of the silicon substrate is in a plane that is about 9°

off a (100) plane;

the side walls of the recess are inclined planes including a plane forming an angle of 45°

with the bottom of the recess; and

the semiconductor element is a semiconductor light emitting element mounted on the electrode at such a position that light emitted from the element is parallel to the bottom of the recess and reflected at the 45°

inclined plane to be perpendicular to the surface of the silicon substrate.

9. The semiconductor device of claim 1 wherein the recess has a shape in the surface of the substrate of two intersecting legs and the element region and wire bonding regions are located in different legs.

5. A semiconductor device comprising:

a silicon substrate having a surface in a plane about 9°

off a (100) plane, and a recess 20-150 μ

m deep at the surface, the recess having a bottom and a plurality of side walls having respective angles of inclination with respect to the bottom of the recess;

an electrode disposed on a region including an element region at the bottom of the recess where a semiconductor element is to be mounted, on a wire bonding region at the surface of the substrate outside the recess where a wire is to be bonded, and on the side wall having the smallest of the angles of inclination with respect to the bottom of the recess;

a semiconductor element mounted on a portion of the electrode within the element region; and

a wire bonded to a portion of the electrode within the wire bonding region.

6. The semiconductor device of claim 5 wherein the electrode is disposed on a region including the element region, the wire bonding region, and at least two side walls of the recess including the side wall having the smallest angle of inclination.

7. The semiconductor device of claim 5 wherein:

the substrate has a convex portion 5˜

20 μ

m high in the recess; and

the element region is on the convex portion.

8. The semiconductor device of claim 5 wherein:

the substrate has a convex portion 5˜

20 μ

m high at the bottom of the recess, the convex portion abutting the side wall having the smallest angle of inclination; and

the electrode is disposed on the element region on the convex portion, the side wall having the smallest angle of inclination and adjacent to the convex portion, and a wire bonding region at the surface of the substrate outside the recess and adjacent to the side wall having the smallest angle of inclination.

10. The semiconductor device of claim 5 wherein the recess has a shape in the surface of the substrate of two intersecting legs and the element region and wire bonding regions are located in different legs.