Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area

• US 5,744,858 A
• Filed: 09/26/1996
• Issued: 04/28/1998
• Est. Priority Date: 07/17/1992
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Rostoker, Michael D.
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/720,219
• Time in Patent Office: 579 Days
• Field of Search: 257/666, 257/690, 257/692, 257/693-697, 257/723, 257/724, 257/730, 257/668, 257/678
• US Class Current: 257/666
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48455 Details of wedge bonds
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/4912 Layout
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49558 : Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10S 148/028 : Dicing

Abstract

A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.

Claims

1. A semiconductor device assembly, comprising:

a semiconductor die having bond pads;

a patterned layer of conductive lines, inner ends of the conductive lines defining an area for receiving the die; and

a body formed about the die and inner ends of the conductive lines, the body having a triangular shape defined by angles alpha, beta and phi, wherein one of the angles is substantially equal to 90°

.

2. A semiconductor device assembly, according to claim 1, wherein:

the angles alpha, beta and phi are 90°

, 45°

, and 45°

, respectively.

3. A semiconductor device assembly, according to claim 1, wherein:

the angles alpha, beta and phi are 90°

, 60°

, and 30°

, respectively.

4. A semiconductor device assembly comprising:

a semiconductor die having bond pads;

a patterned layer of conductive lines having inner and outer ends, the inner ends of the conductive lines defining an area for receiving the die; and

a body formed about the die and the inner ends of the conductive lines, the body having an external surface with the outer ends of the conductive lines thereon, and the body having a non-rectangular parallelogram shape.

5. A semiconductor device assembly, according to claim 4, further comprising:

external pins arranged on the external surface of the body and connected to the outer ends of the conductive lines.

6. A semiconductor device assembly, according to claim 4, further comprising:

ball bumps arranged on the external surface of the body and connected to the outer ends of the conductive lines.

7. An electronic system, comprising:

a printed circuit mother board;

at least two semiconductor device assemblies disposed on the printed circuit mother board, each of the semiconductor device assemblies comprising;

a semiconductor die having bond pads;

a patterned layer of conductive lines having inner and outer ends, the inner ends of the conductive lines defining a an area for receiving the die; and

a body formed about the die and the inner ends of the conductive lines, the body having an external surface with the outer ends of the conductive lines thereon, and the body having a non-rectangular parallelogram shape.