Enhanced defect elimination process for electronic assemblies via application of sequentially combined multiple stress processes

• US 5,744,975 A
• Filed: 06/06/1996
• Issued: 04/28/1998
• Est. Priority Date: 06/06/1996
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cozzolino, Vincent, Notohardjono, Budy Darmono
• Primary Examiner(s): Karlsen, Ernest F.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US08/660,621
• Time in Patent Office: 691 Days
• Field of Search: 324/760, 324/765, 324/158.1, 73/571
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2817 Environmental-, stress-, or burn-in tests of IC's G01R31/2855; of individual semiconductors G01R31/2642; of other circuits G01R31/2849
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2881 related to environmental aspects other than temperature, e.g. humidity or vibrations

Abstract

A method for testing electronic assemblies having an electronic component affixed via solder or other such connections to a printed circuit board. The method includes combining, in order, three sequential stress test steps, into a single stress test for screening defects in the electronic assemblies. In particular, the test combines a thermal cycling stress test followed by a electrical burn-in stress test coupled with functional monitoring of the assembly, followed by a random vibration stress test coupled with functional monitoring of the assembly, each test is imposed with defined parameters upon the electronic assembly. The combination, order, and parameters of the sequential stress test steps provide a single test for electrical assemblies which substantially screens all such assemblies having systematic or random defects while imparting minimal reduction in useful life to the defect-free assemblies by virtue of the testing, thereby resulting in a high reliability product.

Claims

1. A method for detecting defects in an electronic assembly including at least one electronic component, coupled via at least one connection point to a printed circuit board, said method comprising the sequentially ordered steps of:

first performing and completing a temperature cycling test upon the electronic assembly and then;

second performing and completing an electrical burn-in test upon the electronic assembly; and

then

third performing and completing a random vibration test upon the electronic assembly;

wherein each of the sequential test steps are performed and completed separately from the other test steps.

2. A method according to claim 1 wherein the performance of said temperature cycling test step, said electrical burn-in test step, and said random vibration test step cause a minimal reduction in the useful life of said electronic assembly being tested.

3. A method according to claim 1 wherein said defects which are detected include defective ones of said at least one connection points.

4. A method according to claim 1 wherein said defects which are detected include defective ones of said at least one electronic components.

5. A method according to claim 1 wherein said defects which are detected include defects in said printed circuit board.

6. A method according to claim 1 wherein a plurality of electronic assemblies constituting a production volume of said electronic assemblies is tested for detecting defects therein, and any of said plurality of electronic assemblies which are not substantially free from defects are repaired or discarded from said production volume.

7. A method according to claim 1 wherein said temperature cycling test step further includes the steps of:

A. lowering the temperature surrounding the electronic assembly to a predetermined low temperature at a predetermined rate;

B. subjecting said electronic assembly to said predetermined low temperature for a predetermined time period;

C. raising the temperature surrounding the electronic assembly to a predetermined high temperature at said predetermined rate;

D. subjecting said electronic assembly to said predetermined high temperature for said predetermined time period;

E. repeating steps A through D for a predetermined number of times;

F. lowering the temperature surrounding the electronic assembly to room temperature at said predetermined rate; and

G. powering on the electronic assembly at room temperature to determine whether it functions properly.

8. A method according to claim 7 wherein the predetermined low temperature is within a range of temperatures from -40°

C. through -50°

C., the predetermined high temperature is within a range of temperatures from 60°

C. through 70°

C., and the predetermined rate is within a range of rates from 5°

C. per minute through 20°

C. per minute.

9. A method according to claim 8 wherein for step A through step B, the temperature surrounding the electronic assembly is first lowered to -50°

C. and thereafter raised to -40°

C. and maintained at -40°

C. for the remainder of said predetermined time period and wherein for step C through step D, the temperature surrounding the electronic assembly is first raised to 70°

C. and thereafter lowered to 60°

C. and maintained at 60°

C. for the remainder of said predetermined time period.

10. A method according to claim 8 wherein the predetermined time period is 30 minutes.

11. A method according to claim 7 wherein said predetermined total number of times is five.

12. A method according to claim 1 wherein said electrical burn-in test step further includes the steps of:

A. powering the electronic assembly on with a predetermined percentage of a maximum electrical load and repairing or discarding said electronic assembly if it is incapable of being powered on;

B. raising the temperature surrounding the powered-on electronic assembly to a predetermined test temperature at a predetermined rate and maintaining the temperature surrounding the electronic assembly at said predetermined test temperature for a period of time;

C. powering off the electronic assembly and maintaining the temperature surrounding the electronic assembly at said predetermined test temperature for said period of time, thereby providing a power on/off cycle for said electronic assembly having a duration equal to two of said periods of time;

D. repeating steps A through C while functionally monitoring said electronic assembly for defects, until said duration of said repeated power on/off cycles is equal to a cumulative power on/off cycle duration;

E. subjecting the powered on electronic assembly to said predetermined test temperature for a duration equal to said cumulative power on/off cycle duration while functionally monitoring said electronic assembly for defects;

F. repeating steps D through E until the duration of said electrical burn-in test step is between 11 through 22 hours;

G. lowering the temperature surrounding the electronic assembly to room temperature at said predetermined rate; and

H. discarding or repairing the electronic assembly if defects are detected during the functional monitoring in steps D and E.

13. A method according to claim 12 wherein said predetermined percentage of said maximum electrical load is between 50% to 100% of said maximum electrical load specified for said electronic assembly, said predetermined test temperature is a temperature in a range from 40°

C. to 70°

C., said predetermined rate is within a range of rates from 5°

C. per minute through 20°

C. per minute, and wherein said period of time is between 15 minutes through 30 minutes, and said cumulative power on/off cycle duration is 2 hours.

14. A method according to claim 12 wherein said electronic assembly includes at least one power line and at least one sense line, and wherein said functional monitoring of said electronic assembly in steps D and E includes monitoring for electrical signal abnormalities on said at least one power line and on said at least one sense line of the electronic assembly while functionally exercising the electronic assembly to ensure that it functions properly.

15. A method according to claim 14 wherein said electrical signal abnormalities include electrical signals on said at least one monitored power line and said at least one monitored sense line that have logical states that differ from a set of expected logical states for said electrical signals on said at least one monitored power line and said at least one monitored sense line, based upon the functional exercising of the electronic assembly.

16. A method according to claim 14 wherein said signal abnormalities have a duration of at least one millisecond.

17. A method according to claim 12 wherein said functional monitoring in steps D and E is performed at least hourly.

18. A method according to claim 1 wherein said random vibration test step further includes the steps of:

A. vibrating said electronic assembly about a first axis at a predetermined power spectral density within a predetermined range of frequencies for a predetermined duration while functionally monitoring said electronic assembly for defects;

B. vibrating said electronic assembly about a second axis at said predetermined power spectral density within said predetermined range of frequencies for said predetermined duration while functionally monitoring said electronic assembly for defects;

C. inspecting by visual inspection the electronic assembly for physical defects; and

D. discarding or repairing the electronic assembly if defects are detected during the functional monitoring in steps A and B or during the inspecting by visual inspection for physical defects in step C.

19. A method according to claim 18 wherein said first axis is perpendicular to said second axis.

20. A method according to claim 19 wherein prior to step C said random vibration test step further includes the step of vibrating said electronic assembly about a third axis perpendicular to said first axis and said second axis at said predetermined power spectral density for said predetermined duration within said predetermined range of frequencies while functionally monitoring said electronic assembly for defects.

21. A method according to claim 18 wherein said predetermined first axis is the axis about which the electronic assembly is to be mounted when in normal operating use and said second axis is perpendicular to said first axis and perpendicular to the of the surface electronic assembly.

22. A method according to claim 18 wherein said predetermined power spectral density is between 0.005 g² /Hz and 0.04 g² /Hz and wherein said predetermined frequency range is from 10 Hz to 1000 Hz and said predetermined duration is 10 minutes.

23. A method according to claim 22 wherein said predetermined power spectral density is 0.03 g² /Hz for frequencies between 10 Hz through 60 Hz within said predetermined frequency range and said power spectral density is 0.01 g² /Hz for frequencies between 70 Hz through 1000 Hz within said predetermined frequency range.

24. A method according to claim 18 wherein said electronic assembly includes at least one power line and at least one sense line and wherein said functional monitoring of said electronic assembly in steps A and B includes monitoring for electrical signal abnormalities on said at least one power line and on said at least one sense line of the electronic assembly while functionally exercising the electronic assembly to ensure that it functions properly.

25. A method according to claim 24 wherein said electrical signal abnormalities include electrical signals on said at least one monitored power line and said at least one monitored sense line that have logical states that differ from a set of expected logical states for said electrical signals on said at least one monitored power line and said at least one monitored sense line, the expected logical states based upon the functional exercising of the electronic assembly.

26. A method according to claim 24 wherein said signal abnormalities have a duration of at least one millisecond.

27. A method according to claim 18 wherein if, in step C, a physical defect is detected, step D further includes the steps of:

D.1. repairing the electronic assembly; and

D.2. repeating, in said ordered sequence said temperature cycling test step, said electrical burn-in test step and said random vibration test step; and

wherein if a physical defect is detected after said repeated step C, the electronic assembly is discarded.

28. A method according to claim 27 wherein if a physical defect is not detected in repeated step C the electronic assembly is tracked during its field usage.