FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses

• US 5,744,979 A
• Filed: 06/03/1996
• Issued: 04/28/1998
• Est. Priority Date: 07/23/1992
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Goetting, F. Erich
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/656,753
• Time in Patent Office: 694 Days
• Field of Search: 326/39-41, 326/47
• US Class Current: 326/39
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories

Abstract

An FPGA combines antifuse and static memory cell programing technologies. Static memory cells determine the functions of the FPGA logic cells. Antifuses establish routing through the interconnect structure. Associated with each logic cell are configuration control units which store configuration information which configures the cell during normal operation. Each configuration control unit includes an SRAM memory cell. For each input terminal of a logic cell an SRAM configuration control unit selects whether an input signal is inverted or not. Other SRAM cells control whether a signal is cascaded into the logic cell from an adjacent cell, whether the cell operates as a combinational element or a latch, and whether the cell performs NOR or NAND functions. In a preferred embodiment, the configuration control units are used for three purposes: first for applying programing voltages to antifuses in the interconnect structure, second for storing configuration information which configures the cell during normal operation, and third for allowing a user to capture the status of all signals on interconnect lines and shift these out of the chip to be examined by the user.

Claims

1. A programmable integrated circuit comprising:

a plurality of logic elements, each logic element having a plurality of input leads and at least one output lead;

a group of interconnect lines;

a plurality of antifuses for programmably connecting said input and output leads of said logic elements to each other through said interconnect lines;

a plurality of static memory cells for causing said logic elements to perform a selected logic function; and

antifuse programming means programming said antifuses.

2. A programmable integrated circuit as in claim 1 further comprising:

structure for protecting transistors in said static memory cells during programming of said antifuses.

3. A programmable integrated circuit as in claim 2 wherein said structure for protecting transistors in said static memory cells during programming of said antifuses comprises:

structure for preventing said transistors from acting as back biased diodes during programming of said antifuses.