CMOS current source circuit

• US 5,744,999 A
• Filed: 01/22/1996
• Issued: 04/28/1998
• Est. Priority Date: 09/27/1995
• Status: Expired due to Term

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Cho, Sung Ho, Kim, Daejeong
• Primary Examiner(s): Wambach, Margaret Rose
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US08/589,677
• Time in Patent Office: 827 Days
• Field of Search: 323/313, 323/315, 323/312, 327/403, 327/404, 327/416, 327/538, 327/543, 327/545, 327/546, 327/513, 327/108
• US Class Current: 327/543
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G05F 3/245 producing a voltage or current as a predetermined function of the temperature
• CPC Class Codes: G05F 3/247 producing a voltage or current as a predetermined function of the supply voltage
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

An improved CMOS current source circuit capable of constantly generating a certain reference voltage irrespective of an analog supplying voltage, a substrate temperature, and a temperature variation, which includes a start unit for driving the CMOS current source circuit in accordance with a start signal; a bias current generating unit driven by the start unit for generating a bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation; a current input unit for inputting a bias current; and a current compensation unit for receiving a bias current through the current input unit and for compensating the bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation and for generating a reference current.

Claims

1. A current source circuit comprising:

a bias current generating circuit having a first current mirror to generate a bias current in response to a first signal;

a current compensation unit coupled to receive said bias current and having first, second and third transistors, said first transistor generating an offset current such that a first current flowing through said second transistor remains substantially constant, wherein said third transistor is coupled to said second transistor, and a reference current, which is substantially constant, flows through said third transistor; and

a current input unit to provide the bias current to said current compensation unit.

2. The circuit of claim 1, wherein said bias current generating circuit further comprises fourth and fifth transistors and a resistor, wherein said fourth and fifth transistors are coupled to said first current mirror, said resistor and one another.

3. The circuit of claim 1, wherein said bias current generating circuit includes:

a fourth transistor having first and second electrodes and a control electrode;

a fifth transistor having first and second electrodes and a control electrode; and

a resistor coupled to the control electrode of said fifth transistor and said first electrode of said fourth transistor, wherein

the second electrode of said fifth transistor is coupled to the control electrode of said fourth transistor and said first current mirror, and said second electrode of said fourth transistor is coupled to the current mirror.

4. The circuit of claim 2, wherein said first current mirror comprises:

a sixth transistor having first and second electrodes and a control electrode, the first electrode being coupled to receive the first signal and being coupled to said fourth and fifth transistors;

a seventh transistor having first and second electrodes and a control electrode, its control electrode being coupled to its second electrode and said fourth transistor; and

an eighth transistor having first and second electrodes and a control electrode, its control electrode being coupled to said seventh transistor, and providing the bias current at its second electrode.

5. The circuit of claim 3, wherein said current mirror comprises sixth, seventh and eighth transistors coupled in a current mirror configuration with control electrodes of said sixth and seventh transistors being commonly coupled, and said eighth transistor is coupled to said seventh transistor, said sixth transistor being coupled to said fourth and fifth transistors and said seventh transistor being coupled to said fourth transistor, and said eighth transistor providing the bias current.

6. The circuit of claim 1, wherein said current input unit comprises a ninth transistor coupled to receive the bias current and providing the bias current to said first and second transistors in response to the bias current.

7. The circuit of claim 1, wherein said current compensation unit further comprises an eleventh transistor coupled to said second and third transistors.

8. The circuit of claim 7 further comprising a current input unit including ninth and tenth transistors, each having first and second electrodes and a control electrode, the control electrodes of said ninth and tenth transistors being commonly coupled to receive the bias current, wherein

the first electrode of said ninth transistor is coupled to said first and second transistors, and the second electrode of said ninth transistor is coupled to receive the bias current, and

the first electrode of said tenth transistor is coupled to said eleventh transistor.

9. The circuit of claim 8, wherein said eleventh transistor has first and second electrodes and a control electrode, the second electrode of said eleventh transistor being coupled to its control electrode, said tenth transistor and said third transistor, and the control electrode of said eleventh transistor being coupled to said second transistor.

10. The circuit of claim 9, wherein the reference current has a magnitude which is proportional to the first current flowing through said second transistor.

11. The circuit of claim 10, wherein said second and eleventh transistors form a second current mirror.

12. The circuit of claim 1, wherein said first transistor includes first and second electrodes, and a control electrode, its first electrode being coupled to a substrate terminal and coupled to receive said bias current, and its second and control electrodes are coupled to each other.

13. The circuit of claim 1 further comprising a start unit coupled to said bias current generating circuit to generate said first signal, said start unit having

an inverter to receive an external start signal;

and

a twelfth transistor coupled to said inverter and said first current mirror to provide said first signal to said bias current generating circuit.

19. The circuit of claim 2, wherein said resistor has a positive temperature coefficient.

20. The circuit of claim 2, wherein said offset current is adjusted by controlling a ratio of a channel of said first transistor.

21. The circuit of claim 2, wherein said first transistor is a PMOS transistor.

14. A current source circuit comprising:

a) a bias current generating circuit having

i) a first current mirror to generate a bias current in response to a first signal,

ii) a first resistor coupled to said first current mirror, and

iii) a first field effect transistor coupled to said first resistor and said first current mirror; and

b) a current compensating unit receiving said bias current generated by said first current mirror, said current compensation unit having

i) a second current mirror,

ii) means for offsetting current variations of said bias current, said bias current being split between said means and said second current mirror, said means generating an offset current which offsets variations in said bias current such that a first current flowing through said second current mirror remains substantially constant, and

iii) a second field effect transistor coupled to said second current mirror, and a reference current, proportional to said first current, flowing through said second field effect transistor, such that said reference current is substantially constant.

15. The circuit of claim 14, wherein said offset current generating means comprises one of

a) a third field effect transistor when said first resistor has a positive temperature coefficient, and having a gate and drain commonly coupled and a substrate terminal coupled to a source for compensating said bias current, and

b) a second resistor when said first resistor has a negative temperature coefficient.

16. The circuit of claim 14, wherein said bias current generating means further comprises a fourth field effect transistor coupled to said first current mirror, said first field effect transistor and said first resistor.

17. The circuit of claim 14 further comprising a current input unit coupled to said bias current generating circuit for providing said bias current to said current compensation unit, said current input unit having fifth and sixth field effect transistors, each having first and second electrodes and a control electrode, the control electrodes of said fifth and sixth field effect transistors being commonly coupled to receive the bias current, wherein

the first electrode of said fifth transistor is coupled to said offset current generating means and said second current mirror, and the second electrode of said fifth field effect transistor is coupled to said first current mirror for receiving the bias current, and

the first electrode of said sixth field effect transistor is coupled to said second current mirror and said second field effect transistor.

18. The circuit of claim 14 further comprising a start unit coupled to said bias current generating circuit to generate said first signal, said start unit having

an inverter to receive an external start signal;

and

a seventh transistor coupled to said inverter and said first current mirror to provide said first signal to said bias current generating circuit.