Data recovery phase locked loop

• US 5,745,011 A
• Filed: 06/05/1996
• Issued: 04/28/1998
• Est. Priority Date: 06/05/1996
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scott, Paul H.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/658,760
• Time in Patent Office: 692 Days
• Field of Search: 331/44, 331/DIG. 2, 331/17, 331/11, 331/14, 327/160
• US Class Current: 331/44
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A clock recovery phase locked loop system is described. One embodiment has a voltage controlled oscillator divider (the signal of which is compared with a REFCLK divider signal), a voltage stimulus input where a test voltage is applied, a time stimulus input where a digital input with appropriate pulse width is applied and a monitor (output) where the results of the measurement can be observed. A test system is included which applies a series of analog voltages to the voltage stimulus input. For each analog voltage, the test system apply a series of pulses to the time stimulus input. By monitoring (a) the level on the monitor output and (b) the time at which it switches, the VCO gain can be calculated. This allows a direct measurement of VCO gain (K_v) using conventional automatic test equipment used to test digital logic or memory devices.

Claims

1. A phase locked loop system having a detector, a filter and an oscillator along with a reference divider and a comparator having an input and an output comprising:

means for applying a test voltage at a first access node, located between the filter and the oscillator;

means for applying a digital input at an external pin between the reference divider and said comparator including means for applying a series of digital pulses;

means for providing a second input at said external pin comprising a multiplexer; and

means for providing a measurable output connected to said comparator.

2. The phase locked loop circuit according to claim 1 wherein said means for applying a test voltage comprises a voltage stimulus input.

3. The phase locked loop circuit according to claim 2, wherein said voltage stimulus input includes a second access node connected to an output of the filter through a multiplexer.

4. The phase locked loop circuit according to claim 1 wherein said means for applying a digital input comprises a time stimulus input.

5. The phase locked loop circuit according to claim 4 wherein said time stimulus input includes means for providing a series of digital pulses for each analog voltage provided by said means for providing a series of analog voltages.

6. The phase locked loop circuit according to claim 1 wherein said means for applying a digital input includes means for providing a second input.

7. A method for measuring one or more internal parameters in a phase locked loop circuit (PLL), comprising the steps of:

applying a test input to the PLL;

presenting a digital signal having a predetermined pulse width to the PLL; and

displaying an output from the PLL, wherein said digital signal is presented to a comparator in said PLL and said output is displayed from said comparator.

8. The method of claim 7, wherein said step of applying a test voltage comprises supplying a series of analog voltages.

9. The method of claim 7, wherein said step of presenting a digital signal comprises supplying a series of digital pulses for each analog voltage supplied.

10. A phase locked loop circuit comprising:

a detector having an detector input, a feedback input and one or more outputs capable of providing a phase difference signal in response to a phase difference between signals at said detector input and said feedback input;

a filter configured to receive said phase difference signal and to produce a correction signal, said filter having an output;

an oscillator capable of receiving said correction signal, providing said feedback signal, and providing an oscillator signal having a predetermined frequency;

a comparator having a first input configured to receive said oscillator signal and a second input configured to receive a reference signal, said comparator configured to generate an indication signal when said feedback signal and said reference signal have different frequencies;

a voltage stimulus input between said filter and said oscillator, wherein said voltage stimulus input (a) has a first access node connected to said filter output and (b) is capable of applying a test voltage; and

a second access node configured to present a time stimulus input comprising a series of digital pulses with a predetermined pulse width to said second input of said comparator.

11. The phase locked loop circuit according to claim 10, further comprising:

a reference divider configured to receive said reference signal and to generate a modified reference signal at said second input of said comparator.

12. The phase locked loop circuit according to claim 11 wherein said first access node provides a series of analog voltages.

13. The phase locked loop circuit according to claim 12 further comprising a multiplexer configured to receive inputs from a plurality of additional access nodes, each configured to apply additional analog voltages to said voltage stimulus.