Gain calibration circuitry for an analog to digital converter

• US 5,745,060 A
• Filed: 02/12/1996
• Issued: 04/28/1998
• Est. Priority Date: 02/12/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: O'Dowd, John, McCartney, Damien
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/600,313
• Time in Patent Office: 806 Days
• Field of Search: 341/120, 341/142, 341/172
• US Class Current: 341/120
• CPC Class Codes: H03M 3/38 Calibration
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path

Abstract

A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.

Claims

1. A delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;

an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node.

2. A delta sigma modulator, comprising:

an integrating amplifier circuit, having an integrating capacitor, for producing an output indicative of an amount of charge held on the integration capacitor;

a feedback sampling section for, during a calibration mode, sampling a feedback signal and for transferring charge packets corresponding to such sampled voltage to the integrating capacitor;

an input sampling section for, during the calibration mode, sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the integrating capacitor.

3. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:

sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor; and

,

sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor.

4. A delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;

an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.

5. A delta sigma modulator, comprising:

an integrating amplifier circuit, having an integrating capacitor, for producing an output indicative of an amount of charge held on the integration capacitor;

a feedback sampling section for, during a calibration mode, sampling a feedback signal and for transferring charge corresponding to such sampled voltage to the integrating capacitor;

an input sampling section for, during the calibration mode, sampling a calibration voltage each modulator cycle and transferring charge corresponding to a fractional portion of the calibration voltage to the summing node over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.

6. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:

sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor; and

,

sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.

7. A delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node each modulator cycle;

an input signal sampling section having a plurality of capacitors for, during a calibration mode, sampling a calibration voltage with a fractional portion of the plurality of capacitors and transferring charge packets representative of the sampled calibration voltage to the summing node, and for sampling an input voltage, A_IN, during a normal operating mode with the plurality of capacitors and transferring change representative of the input voltage to the summing node.

8. A delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node each modulator cycle;

an input signal sampling section having a plurality of capacitors for, during a calibration mode, sampling a calibration voltage with a portion of the plurality of capacitors and transferring charge packets representative of the sampled calibration voltage to the summing node, and for sampling an input voltage, A_IN, during a normal operating mode with the plurality of capacitors and transferring change representative of the input voltage to the summing node; and

,

wherein the calibration voltage is sampled by a different one of the plurality of capacitors over a corresponding different portion of a period of time, T, the plurality of capacitors sampling the calibration voltage over the period of time T.

9. An delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node in each modulator cycle;

an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node in each modulator cycle.

10. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:

sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle; and

,

sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor in each modulator cycle.

11. A delta sigma modulator, comprising:

a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;

an input signal sampling section having a plurality of, N, capacitors for, during a normal mode, simultaneously sampling an input voltage with the plurality of, N, capacitors producing N charge packets and transferring the N charge packets to the summing node and, during a calibration mode, simultaneously sampling a calibration voltage with a subset, n, of the N plurality of capacitors, where n is less than N, producing n charge packets and transferring the n charge packets to the summing node.

12. The delta sigma modulator recited in claim 11 wherein n=1.

13. The delta sigma modulator recited in claim 11 wherein during each of the samplings of the calibration voltage, the subset of capacitors includes a different one, or ones, of the N capacitors, and wherein each of the N capacitors is included in at least one of the samplings of the calibration voltage.