DC-to-DC converter functioning in a pulse-skipping mode with low power consumption and PWM inhibit
First Claim
1. A method for reducing switching losses in a DC-to-DC converter with a current mode PWM control loop when idle which comprises fixing a certain minimum threshold value of the current flowing through the inductor of the converter, below which the overall switching frequency is reduced, inhibiting any intervening turn-off command of the switch of the converter by the PWM control loop as long as the current through the inductor remains below said minimum threshold value.
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Abstract
Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.
94 Citations
20 Claims
- 1. A method for reducing switching losses in a DC-to-DC converter with a current mode PWM control loop when idle which comprises fixing a certain minimum threshold value of the current flowing through the inductor of the converter, below which the overall switching frequency is reduced, inhibiting any intervening turn-off command of the switch of the converter by the PWM control loop as long as the current through the inductor remains below said minimum threshold value.
- 8. A DC-to-DC static converter composed of a power section which comprises at least a switch driven at a switching frequency set by a clock or local oscillator signal, an inductor, a discharge diode, an output storage capacitor, a PWM control loop suitable to control the duty-cycle of said switch by commanding the turning off in function of the current level in the inductor and of the output voltage of the converter, and a control circuit for reducing the overall switching frequency during idle periods as long as the current in the inductor remains below a minimum threshold value set by a comparator, comprising logic means capable of inhibiting any turn-off command of said PWM control loop switch of the converter for as long as the current in the inductor remains below said minimum threshold value.
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11. A method for operating a power converter, comprising the steps of:
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(A.) sensing the level of output to a load; (B.) under normal load conditions, operating a pulse-width modulator circuit, in dependence on said sensing step (A.), to switch a switching transistor which drives an inductor, and thereby provide at least a desired level of output to the load; and (C.) under low load conditions, inhibiting turn-off of said transistor is inhibited for as long as the current through said inductor is below a threshold value;
whereby switching losses are minimized. - View Dependent Claims (12, 13, 14, 15)
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16. A power converter circuit comprising:
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a load connection for applying an electrical power output to a load; at least one inductor element, and a switching transistor connected to drive said inductor element; sensing circuitry which senses the current through said inductor element; and a pulse-width modulator circuit, operatively connected to receive an input from said sensing element, and operatively connected to repeatedly switch said transistor, under normal conditions, to provide at least a desired level of output to said load connection; and further comprising inhibit logic operatively connected to prevent said transistor from turning off, under low load conditions, for as long as the current through said inductor is below a threshold value. - View Dependent Claims (17, 18, 19)
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20. A static DC-to-DC converter composed of a power section which comprises at least a switch switching at a frequency set by a clock or local oscillator timing signal, an inductor, a discharge diode and an output storage capacitor charged by the discharge current of said inductor, a PWM control loop comprising an error amplifier and a comparator for controlling the duty-cycle of said switch in function of the current in the inductor as detected by a sensing resistance and the output voltage on said storage capacitor, a flip-flop driving said switch and having a "set" input to receive said timing signal and a reset input for receiving a control signal produced by said PWM control loop, at least a second comparator, the inputs of which are functionally connected to said sensing resistance, characterized by comprising
a first OR logic circuit having a first input connected to the output of said second comparator, a second input to which a drive signal of said switch is applied and an output; -
a second AND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to an output of said PWM control loop and an output connected to said reset input of said driving flip-flop; a third NAND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to said set input of said flip-flop and an output; a fourth NAND logic circuit having an input connected to an output of said flip-flop, a second input connected to the output of said third NAND logic circuit and an output connected to a control terminal of said switch.
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Specification