Variable-frequency converter with constant programmed delay

• US 5,745,358 A
• Filed: 12/31/1996
• Issued: 04/28/1998
• Est. Priority Date: 05/01/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Faulk, Richard A.
• Primary Examiner(s): Sterrett, Jeffrey L.
• Application Number:
  US08/775,558
• Time in Patent Office: 483 Days
• Field of Search: 363/21, 363/95, 363/97, 363/131
• US Class Current: 363/95
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H02M 3/33576 having at least one active switching element at the secondary side of an isolation transformer

Abstract

A variable-frequency variable-input-voltage switched-mode power converter, in which a voltage minimum on the primary switching transistor IS estimated as a fixed value which is determined by the time constant of the reactances on the primary side of the converter, and does not vary with the switching frequency. In the presently preferred embodiment, this fixed time-constant-determined delay is used by a secondary-side control subsystem to estimate zero-crossings of the current on the primary side, without using any dissipative current sensing techniques.

Claims

1. A power converter circuit, comprising:

a transformer having primary and secondary windings;

a first controllable switch connected to vary current, from an input voltage connection, through said primary winding;

wherein said input voltage varies substantially continuously;

a power output connection operatively connected to draw power from said secondary winding of said transformer; and

control logic operatively connected to control switching of said switch, with a variable switching frequency, in a control relationship which includes a delay which is independent of the switching frequency, and is not dependent on direct sensing of the current across said switch nor of the current across said primary winding, and is determined by the LC time constant of the inductance of said primary winding in combination with the net capacitance across terminals of said switch.

2. The circuit of claim 1, wherein said power output connections are configured to provide power to a computer system.

3. The circuit of claim 1, wherein said power output connections are configured to provide power to an electrical storage and recharging system.

4. The circuit of claim 1, wherein said first controllable switch is an NMOS transistor.

5. The circuit of claim 1, wherein said first controllable switch is a VDMOS transistor.

6. The circuit of claim 1, wherein said control logic is operatively connected to said secondary winding of said transformer.

7. The circuit of claim 1, wherein said control logic comprises a second controllable switch connected to detect the zero-crossing of current through said secondary winding.

8. The circuit of claim 7, wherein said control logic further comprises a master controller connected to monitor the voltage across said second controllable switch and to control switching of said second controllable switch.

9. The circuit of claim 1, wherein a master controller monitors the zero-crossing of current through said secondary winding through a second controllable switch;

and wherein said master controller monitors said input voltage through an auxiliary winding.

10. The circuit of claim 1, wherein said first controllable switch is controlled by a slave controller;

and wherein a master controller controls the switching signal given by said slave controller.

11. A power conversion method, comprising the steps of:

(a.) repeatedly switching a transistor to switch an input voltage, which varies over a voltage range of at least 3;

1, onto a primary winding of a transformer, while

keeping the frequency of said switching step substantially fixed whenever said input voltage falls within a first range of magnitudes, and

varying the frequency of said switching step in dependence on said input voltage, whenever said input voltage falls within a second range of magnitudes;

wherein said magnitudes of said second range are all greater than said magnitudes of said first range, and

under at least some circumstances, delaying said switching step by a duration which is determined by the LC time constant of the inductance of said primary winding in combination with the net capacitance across terminals of said transistor; and

(b.) coupling power out from said inductance to provide an output of converted power.

12. The method of claim 11, wherein power converted by said method is used to provide power to an electrical storage and recharging system.

13. The method of claim 11, wherein said output of converted power is used to provide power to a computer system.

14. The method of claim 11, wherein said output of converted power is used to provide power to an electrical storage and recharging system.

15. The method of claim 11, wherein power converted by said method is used to provide power to a computer system.

16. The method claim 11, wherein said transistor is an NMOS transistor.

17. The method of claim 11, wherein said transistor is a VDMOS transistor.

18. The method of claim 11, wherein said switching step is controlled by a slave controller, which is controlled by a master controller.

19. A power converter circuit, comprising:

a transformer having primary and secondary windings;

a first controllable switch connected to vary current, from an input voltage connection, through said primary winding;

wherein said input voltage varies substantially continuously;

a power output connection operatively connected to draw power from said secondary winding of said transformer; and

secondary-side control logic operatively connected to draw power from said secondary winding of said transformer, and configured to control switching of said switch in a control relationship which, under at least some circumstances, includes a delay which is proportional to the LC time constant of the inductance of said primary winding in combination with the net capacitance across terminals of said switch.

20. The circuit of claim 19, wherein said power output connections are configured to provide power to a computer system.

21. The circuit of claim 19, wherein said first controllable switch is an NMOS transistor.

22. The circuit of claim 19, wherein said first controllable switch is a VDMOS transistor.

23. The circuit of claim 19, wherein said control logic is operatively connected to said secondary winding of said transformer.

24. The circuit of claim 19, wherein said control logic comprises a second controllable switch connected to detect the zero-crossing of current through said secondary winding.

25. The circuit of claim 24, wherein said control logic further comprises a master controller connected to monitor the voltage across said second controllable switch and to control switching of said second controllable switch.

26. The circuit of claim 19, wherein a master controller monitors the zero-crossing of current through said secondary winding through a second controllable switch;

and wherein said master controller monitors said input voltage through an auxiliary winding.

27. The circuit of claim 19, wherein said first controllable switch is controlled by a slave controller;

and wherein a master controller controls the switching signal given by said slave controller.

28. The circuit of claim 19, wherein said power output connections are configured to provide power to an electrical storage and recharging system.

29. A power conversion method, comprising the steps of repeatedly:

(a.) turning on a switch, which is connected in series with a primary winding of a transformer which also includes a secondary winding inductively coupled to said primary winding, and ramping up current through said switch; and

(b.) turning off said switch, to initiate a current in said secondary winding;

and wherein under at least some circumstances, said turning on step is delayed by a duration which is determined by the LC time constant of the inductance of said primary winding in combination with the net capacitance across terminals of said switch.

30. The method of claim 29, wherein said steps of turning on and turning off is controlled by a slave controller, which is controlled by a master controller.

31. The method of claim 29, wherein said switch is an NMOS transistor.

32. The method of claim 29, wherein said switch is a VDMOS transistor.

33. A computer system, comprising:

memory, and a microprocessor operatively connected to read and write said memory;

a graphics controller connected to said microprocessor;

a video display connected to said graphics controller; and

a transformer having primary and secondary windings;

a first controllable switch connected to vary current, from an input voltage connection, through said primary winding;

wherein said input voltage varies substantially continuously;

a power output connection operatively connected to draw power from said secondary winding of said transformer; and

secondary-side control logic operatively connected to draw power from said secondary winding of said transformer, and configured to control switching of said switch in a control relationship which, under at least some circumstances, includes a delay which is proportional to the LC time constant of the inductance of said primary winding in combination with the net capacitance across terminals of said switch.

34. The system of claim 33, wherein said first controllable switch is an NMOS transistor.

35. The system of claim 33, wherein said first controllable switch is a VDMOS transistor.

36. The system of claim 33, wherein said control logic is operatively connected to said secondary winding of said transformer.

37. The system of claim 33, wherein said control logic comprises a second controllable switch connected to detect the zero-crossing of current through said secondary winding.

38. The system of claim 37, wherein said control logic further comprises a master controller connected to monitor the voltage across said second controllable switch and to control switching of said second controllable switch.

39. The system of claim 33, wherein a master controller monitors the zero-crossing of current through said secondary winding through a second controllable switch;

and wherein said master controller monitors said input voltage through an auxiliary winding.

40. The system of claim 33, wherein said first controllable switch is controlled by a slave controller;

and wherein a master controller controls the switching signal given by said slave controller.