Ferroelectric non-volatile memory

• US 5,745,402 A
• Filed: 11/22/1996
• Issued: 04/28/1998
• Est. Priority Date: 11/24/1995
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Arase, Kenshiro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/755,403
• Time in Patent Office: 522 Days
• Field of Search: 365/145, 365/189.01
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A ferroelectric non-volatile memory which can ensure a sufficient operational margin, wherein memory cells each constituted by a capacitor using a ferroelectric material for the dielectric film and a select transistor are arranged in a matrix to constitute a so-called folded bit-line structure, when reading out data to either a bit line of an even column or a bit line of an odd column, the other bit line is biased to a constant voltage, and, due to this, the coupling noise from adjoining bit lines is shielded.

Claims

1. A ferroelectric non-volatile memory comprising:

at least one first bit line and at least one second bit line arranged adjoining each other in a column direction and together constituting a folded bit-line structure,

a first word line and a second word line arranged in a row direction orthogonal to the folded direction,

a first memory cell constituted by a first ferroelectric capacitor and a first select transistor, one terminal of the first select transistor being connected to the first bit line, another terminal of the first select transistor being connected to one electrode of the first ferroelectric capacitor, and a gate of the first select transistor being connected to the first word line,

a second memory cell constituted by a second ferroelectric capacitor and a second select transistor, one terminal of the second select transistor being connected to the second bit line, another terminal of the second select transistor being connected to one electrode of the second ferroelectric capacitor, and a gate of the second select transistor being connected to the second word line,

a first sense amplifier provided corresponding to the first bit line, and

a second sense amplifier provided corresponding to the second bit line,

wherein, when selecting the first memory cell and reading out its data, the data of the first memory cell is read out to the first bit line with the second bit line being set to a constant shield voltage, a potential of the first bit line and a reference voltage for comparison are compared by the first sense amplifier, and the data of the first memory cell is electronically determined as a result of the comparison and,

when selecting the second memory cell and reading out its data, the data of the second memory cell is read out to the second bit line with the first bit line being set to a constant shield voltage, a potential of the second bit line and a reference voltage for comparison are compared by the second sense amplifier, and the data of the second memory cell is electronically determined as a result of the comparison.

2. A ferroelectric non-volatile memory according to claim 1, wherein

when selecting the first memory cell and reading out its data, the second sense amplifier is deactivated, and

when selecting the second memory cell and reading out its data, the first sense amplifier is deactivated.

3. A ferroelectric non-volatile memory, comprising:

a first memory array constituted by at least one 1a-th bit line and at least one 2a-th bit line arranged adjoining each other in a column direction and together constituting a folded bit-line structure, a 1a-th word line and a 2a-th word line arranged in a row direction orthogonal to the folded direction, a 1a-th memory cell constituted by a ferroelectric capacitor and a select transistor, one terminal of the select transistor being connected to the 1a-th bit line, another terminal of the select transistor being connected to an electrode of the ferroelectric capacitor, and a gate of the select transistor being connected to the 1a-th word line, a 2a-th memory cell constituted by a ferroelectric capacitor and a select transistor, one terminal of the select transistor being connected to the 2a-th bit line, another terminal of the select transistor being connected to one electrode of the ferroelectric capacitor, and a gate of the select transistor being connected to the 2a-th word line, a 1a-th reference cell provided corresponding to the 1a-th bit line, and a 2a-th reference cell provided corresponding to the 2a-th bit line;

a second memory array constituted by at least one 1b-th bit line and at least one 2b-th bit line arranged adjoining each other in a column direction and together constituting a folded bit-line structure, a 1b-th word line and a 2b-th word line arranged in a row direction orthogonal to the folded direction, a 1b-th memory cell constituted by a ferroelectric capacitor and a select transistor, one terminal of the select transistor being connected to the 1b-th bit line, another terminal of the select transistor being connected to one electrode of the ferroelectric capacitor, and a gate of the select transistor being connected to the 1b-th word line, a 2b-th memory cell constituted by a ferroelectric capacitor and a select transistor, one terminal of the select transistor being connected to the 2b-th bit line, another terminal of the select transistor connected to an electrode of the ferroelectric capacitor, and a gate of the select transistor being connected to the 2b-th word line, a 1b-th reference cell provided corresponding to the 1b-th bit line, and a 2b-th reference cell provided corresponding to the 2b-th bit line;

a first sense amplifier comparing a potential of the 1a-th bit line with a potential of the 1b-th bit line and reading out the data; and

a second sense amplifier comparing a potential of the 2a-th bit line with a potential of the 2b-th bit line and reading out the data.

4. A ferroelectric non-volatile memory according to claim 3, wherein

when selecting the 1a-th memory cell and reading out its data, the data of the 1a-th memory cell is read out to the 1a-th bit line with the 2a-th and 2b-th bit lines being set to a constant shield voltage, a potential of the 1a-th bit line and a potential of the 1b-th bit line are compared by the first sense amplifier, and the data of the 1a-th memory cell is electronically determined as a result of the comparison,

when selecting the 2a-th memory cell and reading out its data, the data of the 2a-th memory cell is read out to the 2a-th bit line and the data of the 2b-th reference cell is read out to the 2b-th bit line with the 1a-th and 1b-th bit lines being set to a constant shield voltage, a potential of the 2a-th bit line and a potential of the 2b-th bit line are compared by the first sense amplifier, and the data of the 2a-th memory cell is electronically determined as a result of the comparison,

when selecting the 1b-th memory cell and reading out its data, the data of the 1b-th memory cell is read out to the 1b-th bit line and the data of the 1a-th reference cell is read out to the 1a-th bit line with the 2a-th and 2b-th bit lines being set to a constant shield voltage, a potential of the 1a-th bit line and a potential of the 1b-th bit line are compared by the first sense amplifier, and the data of the 1b-th memory cell is electronically determined as a result of the comparison, and

when selecting the 2b-th memory cell and reading out its data, the data of the 2b-th memory cell is read out to the 2b-th bit line and the data of the 2a-th reference cell is read out to the 2a-th bit line with the 1a-th and 1b-th bit lines being set to a constant shield voltage, a potential of the 2a-th bit line and a potential of the 2b-th bit line are compared by the second sense amplifier, and the data of the 2b-th memory cell is electronically determined as a result of the comparison.

5. A ferroelectric non-volatile memory according to claim 3, wherein

when selecting the 1a-th or 1b-th memory cells and reading out its data, the second sense amplifier is deactivated, and

when selecting the 2a-th or 2b-th memory cell and reading out its data, the first sense amplifier is deactivated.