Integrated circuit system having reference cells for improving the reading of storage cells

• US 5,745,414 A
• Filed: 11/26/1996
• Issued: 04/28/1998
• Est. Priority Date: 09/14/1994
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Information Storage Devices, Inc. (Winbond Electronics Corporation)
• Inventors: Engh, Lawrence D., Blyth, Trevor
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/756,564
• Time in Patent Office: 518 Days
• Field of Search: 365/185.2, 365/211, 365/45, 365/210, 365/185.03
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5624 Concurrent multilevel programming and programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

The present invention is an improvement in an analog storage device having a row of EEPROM cells. The improvement includes providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line. The improvement further includes providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor, wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.

Claims

1. In an analog storage apparatus having a row of EEPROM cells, an improvement comprising:

providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line;

providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor; and

wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.

2. In an analog storage device having a row of storage cells, an improvement comprising:

providing a pair of cells including a first cell and a second cell for storing one of a plurality of analog values, with the first cell being a reference cell and with the second cell being a storage cell, and with a clear gate of a transistor of the reference cell being selectively controlled to compensate for variations in the environment of the storage cell.

3. The improvement of claim 2, wherein the clear gate is controlled to compensate for temperature variations.

4. The improvement of claim 2, wherein the pair of cells comprises of a pair of EEPROM cells.

5. The improvement of claim 2, wherein the first cell comprises of an EEPROM cell.

6. The improvement of claim 2, wherein the second cell comprises of an EEPROM cell.

7. In an analog storage device having rows and columns of storage cells, each row having a row select transistor, an improvement comprising:

providing an additional row select transistor to a group of column cells for isolation of a first plurality of storage cells from a second plurality of storage cells within the group of column cells, whereby a total capacitance on a read-while-writing line connected to said cells is decreased.

8. In an analog storage apparatus having a row of non-volatile cells, an improvement comprising:

providing a reference cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line;

providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor; and

wherein the gate of the first transistor is connected to gates of first transistors of each of the row of non-volatile cells.