Phase-shifted embedded ram apparatus and method
First Claim
1. A random access memory device adapted to operate in connection with a given clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory device occurs during said first phase of said clock cycle, said device comprising:
- a plurality of memory cells, wherein each of said memory cells stores an individual bit of digital data; and
a data bus coupled to said memory cells for providing means to communicate said digital data to and from said memory cells during write and read operations, wherein during a write operation to a designated memory location of said random access memory device, a write access cycle is phase shifted at least one phase later relative said read access cycle.
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Abstract
The present invention is an embedded random access memory device especially adapted for use with digital processors having a pipelined data architecture. In accordance with one embodiment of the present invention a write access cycle performed at a memory location within the memory device is phase shifted by one phase of a clock cycle relative an access cycle of a read operation. This is advantageous in that the integrity of data which traditionally would have been presented late in the write access cycle can still be maintained, since the entire write cycle is now shifted one phase later. A precharge signal which follows the write access is correspondingly shifted by one phase of a clock cycle. A wait state is inserted between the write access cycle and a read access cycle which directly follows in the same memory bank of the memory device. The wait state eliminates conflicts between the access cycle and the precharge cycle.
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Citations
21 Claims
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1. A random access memory device adapted to operate in connection with a given clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory device occurs during said first phase of said clock cycle, said device comprising:
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a plurality of memory cells, wherein each of said memory cells stores an individual bit of digital data; and a data bus coupled to said memory cells for providing means to communicate said digital data to and from said memory cells during write and read operations, wherein during a write operation to a designated memory location of said random access memory device, a write access cycle is phase shifted at least one phase later relative said read access cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit including embedded random access memory therein, said random access memory adapted to operate in connection with a pipeline processor utilizing a clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory occurs during said first phase of said clock cycle, said integrated circuit comprising:
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a plurality of memory cells, wherein each of said memory cells stores an individual bit of digital data; an address bus coupled to said memory cells for providing addresses to access specific ones of said memory cells; and a data bus coupled to said memory cells for providing means to communicate said digital data to and from said memory cells during write and read operations, wherein during a write operation to a designated memory location of said random access memory, a write access cycle is phase shifted one phase later relative said read access cycle. - View Dependent Claims (10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21)
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16. A method of operating an embedded random access memory, said random access memory adapted to operate in connection with a pipeline processor utilizing a clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory occurs during said first phase of said clock cycle, said method including the steps of:
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receiving valid data at a data bus of said random access memory for performing a write operation to a designated memory location therein; and phase shifting a write access cycle to said designated memory location one phase later relative said read access cycle.
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Specification