Phase-shifted embedded ram apparatus and method

• US 5,745,427 A
• Filed: 12/27/1996
• Issued: 04/28/1998
• Est. Priority Date: 12/27/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.), Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Holder, Clinton Hays, Freyman, Ronald Lamar
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/773,706
• Time in Patent Office: 487 Days
• Field of Search: 365/230.01, 365/233, 365/230.03, 365/203, 365/194
• US Class Current: 365/230.01
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

The present invention is an embedded random access memory device especially adapted for use with digital processors having a pipelined data architecture. In accordance with one embodiment of the present invention a write access cycle performed at a memory location within the memory device is phase shifted by one phase of a clock cycle relative an access cycle of a read operation. This is advantageous in that the integrity of data which traditionally would have been presented late in the write access cycle can still be maintained, since the entire write cycle is now shifted one phase later. A precharge signal which follows the write access is correspondingly shifted by one phase of a clock cycle. A wait state is inserted between the write access cycle and a read access cycle which directly follows in the same memory bank of the memory device. The wait state eliminates conflicts between the access cycle and the precharge cycle.

Claims

1. A random access memory device adapted to operate in connection with a given clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory device occurs during said first phase of said clock cycle, said device comprising:

a plurality of memory cells, wherein each of said memory cells stores an individual bit of digital data; and

a data bus coupled to said memory cells for providing means to communicate said digital data to and from said memory cells during write and read operations, wherein during a write operation to a designated memory location of said random access memory device, a write access cycle is phase shifted at least one phase later relative said read access cycle.

2. The device of claim 1, further comprising a charge line for providing a precharge signal to said memory cells, wherein said precharge signal following said write access cycle to said designated memory location is correspondingly phase shifted by said at least phase.

3. The device of claim 1, wherein said plurality of memory cells are divided into two or more banks of memory cells, said designated memory location being located in a first bank of said memory cells, wherein said device is operable to insert a wait state to delay access to a memory location in said first bank of memory cells when a read operation to said first bank of memory cells directly follows said write operation at said designated memory location.

4. The device of claim 3, wherein said wait state is one clock cycle.

5. The device of claim 1, further comprising an address bus coupled to said memory cells for providing addresses to access specific ones of said memory cells.

6. The device of claim 3, further comprising a comparator device coupled to said address bus for determining which of said banks of memory cells will be accessed during a next read or write operation.

7. The device of claim 1, further comprising:

a read/write enable line coupled to said memory cells for indicating a read or write operation at specific ones of said memory cells being accessed.

8. The device of claim 1, wherein said random access memory device is embedded memory adapted for use with a digital processor having a data pipeline architecture.

9. An integrated circuit including embedded random access memory therein, said random access memory adapted to operate in connection with a pipeline processor utilizing a clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory occurs during said first phase of said clock cycle, said integrated circuit comprising:

a plurality of memory cells, wherein each of said memory cells stores an individual bit of digital data;

an address bus coupled to said memory cells for providing addresses to access specific ones of said memory cells; and

a data bus coupled to said memory cells for providing means to communicate said digital data to and from said memory cells during write and read operations, wherein during a write operation to a designated memory location of said random access memory, a write access cycle is phase shifted one phase later relative said read access cycle.

10. The integrated circuit of claim 9, further comprising a charge line for providing a precharge signal to said memory cells, wherein said precharge signal following said write access cycle to said designated memory location is correspondingly phase shifted by said one phase.

11. The integrated circuit of claim 10, wherein said plurality of memory cells are divided into two or more banks of memory cells, said designated memory cell being located in a first bank of said memory cells, wherein said device is operable to insert a wait state to delay access to a memory location in said first bank of memory cells when a read operation to said first bank of memory cells directly follows said write operation at said designated memory location.

12. The integrated circuit of claim 11, wherein said wait state is a single clock cycle.

13. The integrated circuit of claim 12, further comprising a comparator device coupled to said address bus for determining which of said banks of memory cells will be accessed during a next read or write operation.

14. The integrated circuit of claim 11, wherein an access to a memory cell during a read operation to a bank of memory cells other than one experiencing a directly preceding write operation is not delayed by said wait state.

15. The integrated circuit of claim 9, further comprising a digital processor coupled to said random access memory, said processor having a data pipeline architecture.

17. The method of claim 15, further including the step of correspondingly phase shifting a precharge signal following said write access cycle to said designated memory location by said one phase.

18. The method of claim 15, wherein said plurality of memory cells are divided into two or more banks of memory cells, said designated memory location being located in a first bank of said memory cells, further including the step of inserting a wait state to delay access to a memory location in said first bank of memory cells when a read operation to said first bank of memory cells directly follows said write operation at said designated memory location.

19. The method of claim 17, further including the step of comparing addresses on an address bus of said random access memory to determine which of said memory banks will be accessed during a next read or write operation.

20. The method of claim 15, wherein said random access memory device is included in an applications specific integrated circuit.

21. The method of claim 17, wherein said wait state is a single clock cycle.

16. A method of operating an embedded random access memory, said random access memory adapted to operate in connection with a pipeline processor utilizing a clock signal, said clock signal having a first phase and a second phase for each clock cycle thereof, wherein a read access cycle to a memory location of said random access memory occurs during said first phase of said clock cycle, said method including the steps of:

receiving valid data at a data bus of said random access memory for performing a write operation to a designated memory location therein; and

phase shifting a write access cycle to said designated memory location one phase later relative said read access cycle.