Method and system for addressing multiple components on a communication bus

• US 5,745,493 A
• Filed: 11/20/1995
• Issued: 04/28/1998
• Est. Priority Date: 11/20/1995
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: St. Clair, Joe Christopher
• Primary Examiner(s): Marcelo, Melvin
• Application Number:
  US08/560,917
• Time in Patent Office: 890 Days
• Field of Search: 370/257, 370/438, 370/439, 370/449, 370/462, 370/463, 307/41, 340/825.07, 340/825.08, 340/825.52
• US Class Current: 370/438
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

A method and system for sequentially addressing multiple components, having a limited number of externally available address lines, on a communication bus. The method and system employs an addressing scheme in combination with a specific interconnection of the components. This combination enables each of the components to be addressed in a sequential fashion by dynamically altering their address. Thus, allowing a virtually unlimited number of components to be coupled to the communication bus without the traditional concerns over the number of externally available address lines.

Claims

1. A method of addressing a chain of units coupled to a communication bus, said method comprising the steps of:

dynamically altering, in response to receiving a reset command, each one of said units to have a reset address;

dynamically altering, in response to receiving an access command, a first one of said units to have an access address; and

dynamically altering, each time a unit having an access address receives a sequential command, said receiving unit to have a reset address and the next succeeding unit to have said access address.

2. The method of claim 1 further comprising the steps of:

transmitting said reset command to each one of said units; and

transmitting said access command to said first unit.

3. The method of claim 2 wherein said communication bus is a low speed bus.

4. The method of claim 3 wherein said communication bus is the I² C bus.

5. The method of claim 2 wherein each one of said units is accessed sequentially according to their position within said chain.

6. An apparatus having a communication bus for addressing a chain of units coupled to said communication bus, said apparatus comprising:

means for dynamically altering, in response to receiving a reset command, each one of said units to have a reset address;

means for dynamically altering, in response to receiving an access command, a first one of said units to have an access address; and

means for dynamically altering, each time a unit having an access address receives a sequential command, said receiving unit to have a reset address and the next succeeding unit to have said access address.

7. The apparatus of claim 6 further comprising:

means for transmitting said reset command to each one of said units; and

means for transmitting said access command to said first unit.

8. The apparatus of claim 7 wherein said communication bus is a low speed bus.

9. The apparatus of claim 7 wherein said communication bus is the I² C bus.

10. The apparatus of claim 7 wherein each one of said units is accessed sequentially according to their position within said chain.

11. An apparatus comprising:

a communication bus;

a first component, coupled to said communication bus, having a first address line and a first output line coupled one to another;

a second component, coupled to said communication bus, having a first and second address line and a first output line, said second component'"'"'s first address line and first output line being coupled one to another, and said first component'"'"'s first output line being coupled to said second component'"'"'s second address line; and

a third component, coupled to said communication bus, having a first and second address line and a first output line, said third component'"'"'s first address line and first output line being coupled one to another, and said third component'"'"'s second address line being coupled to said second component'"'"'s output line.

12. The apparatus of claim 11 wherein each one of said components include at least two additional available address lines.

13. The apparatus of claim 12 wherein said communication bus is a low speed bus.

14. The apparatus of claim 12 wherein said communication bus is I² C bus.