Built-in self testing for the identification of faulty integrated circuit chips in a multichip module
First Claim
1. A built-in self-test method for the identification of a faulty integrated circuit chip in a multichip module having a plurality of chips, comprising the steps of:
- applying a test pattern to the multichip module, each of the chips being responsive to the test pattern and having at least one output representing a test response;
applying a test pattern to a reference signal generator, the reference signal generator generating first and second reference signals in response thereto, whereby the first and second reference signals represent test responses of a fault free multichip module;
compressing the outputs from the chips into first and second compressed outputs using first and second linear space compressors respectively;
deriving a first fault detection output by adding the first compressed output to the first reference signal using exclusive OR logic;
deriving a second fault detection output by adding the second compressed output to the second reference signal using exclusive OR logic;
storing the first and second fault detection outputs in first and second N-bit shift registers respectively;
comparing the stored outputs in the first and second N-bit shift registers to detect a fault condition; and
applying a series of recursive logic operations to identify the faulty chip.
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Abstract
A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module. The built-in self test circuit includes a test pattern generator, a reference signal generator, at least two linear space compressors, at least two N-bit shift registers, and a plurality of logic gates. Identification of the faulty integrated circuit chip in an multichip module using the present invention thereby facilitates the replacement of the specific faulty chip in order to repair the multichip module.
34 Citations
12 Claims
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1. A built-in self-test method for the identification of a faulty integrated circuit chip in a multichip module having a plurality of chips, comprising the steps of:
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applying a test pattern to the multichip module, each of the chips being responsive to the test pattern and having at least one output representing a test response; applying a test pattern to a reference signal generator, the reference signal generator generating first and second reference signals in response thereto, whereby the first and second reference signals represent test responses of a fault free multichip module; compressing the outputs from the chips into first and second compressed outputs using first and second linear space compressors respectively; deriving a first fault detection output by adding the first compressed output to the first reference signal using exclusive OR logic; deriving a second fault detection output by adding the second compressed output to the second reference signal using exclusive OR logic; storing the first and second fault detection outputs in first and second N-bit shift registers respectively; comparing the stored outputs in the first and second N-bit shift registers to detect a fault condition; and applying a series of recursive logic operations to identify the faulty chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A built-in self-test circuit for the identification of a faulty integrated circuit chip in a multichip module having a plurality of chips, comprising:
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a test pattern generator for applying a test pattern to the multichip module, each of the chips being responsive to the test pattern and having at least one output representing a test response; a reference signal generator, coupled to and responsive to said test pattern generator, for generating first and second reference signals representing test responses of a fault free multichip module; first and second data compression means for compressing the outputs from the chips into first and second compressed outputs respectively; logic means for adding the first compressed output from the first data compression means to the first reference signal to produce a first fault detection output and for adding the second compressed output from the second data compression means to the second reference signal to produce a second fault detection output; first and second means for registering the first and second fault detection outputs respectively, said first and second registering means coupled to said logic means, means for generating a fault identification vector based on the registered fault detection outputs, said generating means coupled to said first and second registering means; means for storing the fault identification vector, said storing means coupled to said means for generating a fault identification vector; and a clock generator for generating a plurality of clock signals to sequentially order the generation of the fault identification vector, said clock generator coupled to said means for storing the fault identification vector. - View Dependent Claims (10, 11, 12)
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Specification