Transmission system via communications protected by an error management code

• US 5,745,509 A
• Filed: 11/17/1995
• Issued: 04/28/1998
• Est. Priority Date: 11/30/1994
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Marchand, Philippe
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US08/559,963
• Time in Patent Office: 893 Days
• Field of Search: 371/43, 371/37.1, 371/38.1, 371/39.1, 371/37.4, 371/43.1, 371/43.5
• US Class Current: 714/786
• CPC Class Codes: G11B 20/1809 by interleaving
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A data transmission system wherein data to be transmitted is supplied to an encoding device (5) which comprises a data analysis circuit (35) for producing a parity code and an output circuit (32) for assigning the parity code to the input data so as to convert it into protected data for transmission. The data analysis circuit includes: (i) a serial-to-parallel converter (30) for converting the input data into "n" parallel data streams, the bits in each stream being at instants which are multiples of n×T, where T is the bit period of the input data; (ii) "n" cascade combinations of delay elements, each cascade delaying one of the "n" parallel-converted data streams by time periods which are multiples of n×T, each cascade having tapping points following certain ones of the delay elements therein; and (iii) combining circuits (GR1, GR2, OE) having inputs connected to tapping points of each of the cascade combinations and which derive the parity code.

Claims

1. A transmission system for successive bit strings of data and which provides error protection by applying an error management code which takes into account, at least twice, the value of each bit;

said system comprising;

an encoding device which has

an input access for input data to be transmitted, the input data having a bit frequency equal to 1/T,

serial-to-parallel converting means for receiving the input data from the input access and having a plurality "n" of outputs at which parallel-converted input data is produced at instants which are multiples of n×

T,

a data analysis circuit for receiving parallel-converted data from said converting means and producing an error management code therefrom, and

an output circuit for producing protected data at an output access thereof by assigning said error management code to the parallel-converted input data;

means for transmitting the protected data; and

a decoding device which has

a receiving access for receiving the transmitted protected data,

an error processing circuit, and

an output access at which data recovered from the received data is produced;

wherein said data analysis circuit comprises

a plurality "n" of cascade combinations of delay elements, each cascade delaying a string of parallel-converted data received from such converting means for time periods which are multiples of n×

T, and

a plurality of combining circuits having inputs connected to at least two tapping points of each of said cascade combinations and which combine data bits present at said tapping points to thereby derive said error management code;

each of said cascade combinations of said data analysis circuit having tapping points following two delay elements therein which are equal to, respectively, (p-j+1)×

(n×

T) and (p+j)×

(n×

T), where j=1 . . . n, and p represents the average total number of delay elements in each of said cascade combinations.

2. A transmission system for successive bit streams of data and which provides error protection by applying an error management code which takes into account, at least twice, the value of each bit, said system comprising:

an encoding device which has

an input access for input data to be transmitted, the input data having a bit frequency equal to 1/T,

serial-to-parallel converting means for receiving the input data from the input access and having a plurality "n" of outputs at which parallel-converted input data is produced at instants which are multiples of n×

T,

a first data analysis circuit for receiving parallel-converted data from said converting means and producing an error management code therefrom, and

an output circuit for producing protected data at an output access thereof by assigning said error management code to the parallel-converted input data;

means for transmitting the protected data; and

a decoding device which has

a receiving access for receiving the transmitted protected data;

an error processing circuit, and

an output access at which decoded data recovered from the received data is produced;

wherein said decoding means comprises;

a distributing circuit for the received data and which separates the transmitted error management code therefrom,

a second data analysis circuit having a plurality "n" of cascade combinations of delay elements to which the received data is distributed by said distributing circuit, and which derives from the data so distributed a local error management code,

a comparing element (P_c) for deriving a comparison signal based on comparison of the transmitted error management code with the local error management code, and

a correction circuit for correcting the received data as a function of said comparison signal in order to derive decoded data from the received data;

each of the cascade combinations of said second data analysis circuit having tapping points following the two delay elements therein which are equal to, respectively, (p-j+1)×

(n×

T) and (p+j)×

(n×

T), where j=1 . . . n, and p represents the average total number of delay elements in each of said cascade combinations.

3. A transmission system for successive bit streams of data and which provides error protection by applying an error management code which takes into account, at least twice, the value of each bit, said system comprising:

an encoding device which has

an input access for input data to be transmitted, the input data having a bit frequency equal to 1/T,

serial-to-parallel converting means for receiving the input data from the input access and having a plurality "n" of outputs at which parallel-converted input data is produced at instants which are multiples of n×

T,

a first data analysis circuit for receiving parallel-converted data from said converting means and producing an error management code therefrom, and

an output circuit for producing protected data at an output access thereof by assigning said error management code to the parallel-converted input data;

means for transmitting the protected data; and

a decoding device which has

a receiving access for receiving the transmitted protected data;

an error processing circuit, and

an output access at which decoded data recovered from the received data is produced;

wherein said decoding means comprises;

a distributing circuit for the received data and which separates the transmitted error management code therefrom,

a second data analysis circuit having a plurality "n" of cascade combinations of delay elements to which the received data is distributed by said distributing circuit, and which derives from the data so distributed a local error management code,

a comparing element (P_c) for deriving a comparison signal based on comparison of the transmitted error management code with the local error management code, and

a correction circuit for correcting the received data as a function of said comparison signal in order to derive decoded data from the received data;

a correction circuit for correcting the received data as a function of said comparison signal, said correction circuit having a plurality "n" of cascade combinations of delay elements for data received from said second data analysis circuit and delaying the received data for time periods which are multiples of n×

T, each of said cascade combinations including data value changers for changing the values of data therein in accordance with said comparison signal;

the data value changers having inputs in said cascade combinations following the delay elements therein equal to (q+1-j)×

(n×

T), where j=1, . . . n, and q represents the average total number of delay elements in each of said cascade combinations.